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June 23, 2011
Flying halfway around the world to just gather news seems like a waste of time in the information age. But when it comes to supercomputing shows like ISC, being there in person cannot be duplicated by the remote experience, despite live streaming sessions, video blogs, and ISC twitter feeds.
Part of that has to do with the fact that information just seems to flow more freely under the chaotic conditions of a busy show floor. The other aspect is that exhibitors assume they're talking to potential prospects, so the vendors tend to be a little looser lipped than I'm used to as a journalist.
For example, although Intel wasn't willing to share with me over email last week that their first Many Integrated Core (MIC) product, aka Knights Corner, would support ECC memory, one person in the Intel booth at ISC did indeed confirm that MIC would be released with such support. (The Knights Ferry prototype is using a vanilla, i.e., non-ECC, graphics memory controller.) Like I mentioned in my original reporting of this week's MIC news, it would be inconceivable not to have ECC support in this HPC product, so no big surprise here.
I also found out that the peak performance on the Knights Ferry prototype is 1.2 single precision (SP) teraflops. Given that the next year's Knights Corner product will be on 22nm technology and will have about twice as many cores, I expect it will at least double that SP floating point teraflops, with maybe half the number for double precision (DP).
The GPU contingent from AMD won't be intimidated from such floppery though. They told me that the next version of the FireStream HPC product will have twice the performance of the current model. The 9350 and 9370 products being shipped today deliver 528 DP gigaflops and 2.64 SP teraflops. The new FireStreams will be announced this fall -- around SC11, I'm guessing -- and will start shipping sometime in early 2012.
Meanwhile NVIDIA says it will deliver its next generation Kepler GPU architecture in 2012, At an ISC presentation by Nvidian Sumit Gupta, he estimated the new GPU will deliver about 5 DP gigaflops per watt, or maybe even better than that. "Kepler is going to be an amazing performance per watt GPU," he promised.
If NVIDIA maintains the same thermal envelope as the current Fermi-class devices (225-250 watts), then the Kepler GPUs will be well north of a double precision teraflop. In fact all three 2012 HPC accelerators look to top one DP teraflop, but it is unlikely that any will reach 2 teraflops. With that kind of performance parity, the competitive differentiators may be energy efficiency and ease of programming.
In the latter case, Intel may have the edge. I heard a number of comments here in Hamburg that MIC is more straightforward to program than a GPU, at least to get an initial, non-optimized port -- not just because it's based on the x86 architecture, but because it lends itself more easily to standard multicore-style programming frameworks, like OpenMP. That indeed will warm the hearts of many application developers, inasmuch as a lots of code is already parallelized with OpenMP.
On the other hand, CUDA remains the more mature software environment for manycore acceleration at this point, and AMD said that the upcoming FireStream offerings will also include more advanced tools, libraries, and drivers. In any case, software development for accelerator programming is bound to get easier over the next year, but the devil will be in the details.
On the energy efficiency front, it looks like all three HPC accelerator offerings will need at least need 200 watts to hit a teraflop. It remains to be seen if Intel, NVIDIA, or AMD will have any appreciable edge.
On the broader topic of energy efficiency, there was lots of chatter at the conference about exascale power budgets. The current goal of US federal agencies is to have an exaflop fit into 20MW. That means to run such a system will cost about $20 million per year in the US and 20 million euros in Europe. Unfortunately, a number of people in the know at ISC thought that was quite an optimistic figure for the first exaflop systems. Estimates for these early machines ranged from as much 40MW (Cray CTO Steve Scott) to 200 MW (LSU prof Thomas Sterling).
The power problem is not a showstopper though. There are 100MW datacenters today and if the political will is there to fund power-sucking monsters at this scale, it could be done. Eventually exaflop systems will use 20MW, and less, but perhaps not the first crop of machines.
On a related note, Japan's March 11 earthquake/tsunami disaster is already forcing that nation's HPC community to deal with reduced power availability. Not that they weren't already focused on energy efficiency. Japanese supercomputing has always had to adhere to strict power budgets since the nation lacks significant indigenous energy resources. But the situation is especially acute right now.
In a presentation at ISC, the University of Tsukuba's Taisuke Boku told the audience that in the wake of the disaster, four one-gigawatt power plants are now offline. According to him, Tokyo residents, businesses, and other organizations (including HPC centers) will be required to cut their power usage by 15 percent this summer because of the downed plants.
Boku said this summer the university's PACS-CS supercomputer will be shut down during the day, from 9:00 am to 9:00 pm, to deal with the power restriction shortage. And this is expected to continue for a number of years while Japan rebuilds its power plant infrastructure. The irony here is that PACS-CS uses low voltage Xeons, so is already is built for energy-efficient operation.
An even bigger irony is that the Japanese K Computer, which captured the number one spot on the TOP500 list is using about 10MW. The fact that an 8-petaflop machine uses half the 20MW that people are aiming for in an exaflop machine should be sobering enough. The bigger problem though is that power consumption for the top systems is increasing faster than gains in energy efficiency. As we say in the HPC biz, that doesn't scale.
I actually have more to report from my Hamburg excursion, including some interesting developments to create net zero carbon HPC datacenters. But that will have to wait for another time.
Posted by Michael Feldman - June 23, 2011 @ 2:42 PM, Pacific Daylight Time
Michael Feldman is the editor of HPCwire.
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