NCSA
HPCwire

Since 1986 - Covering the Fastest Computers
in the World and the People Who Run Them

Language Flags

Visit additional Tabor Communication Publications

Datanami
Digital Manufacturing Report
HPC in the Cloud
Green Computing Report
HPCwire Japan

Tabor Communications
Corporate Video

Blog: From the Editor

From the Editor | Main Blog Index

Researchers Spin Up Supercomputer for Brain Simulation


Under the category of "Grand Challenge" applications, perhaps none is grander than simulation of the human brain. Reflecting the complexity and scale of the brain with current computer technology is truly a daunting task. But a group of researchers and computer scientists at a number of UK universities are attempting to do just that under a project named SpiNNaker.

SpiNNaker, which stands for Spiking Neural Network architecture, aims to map the brain's functions for the purpose of helping neuroscientists, psychologists and doctors understand brain injuries, diseases and other neurological conditions. The project is being run out of a group at University of Manchester, which designed the system architecture, and is being funded by a £5m grant from the Engineering and Physical Sciences Research Council (EPSRC). Other elements of the SpiNNaker system are being developed at the universities of Southampton, Cambridge and Sheffield.

For the casual observer, constructing a facsimile of the most complex organ in the human body from digital technology may see like a natural fit for computers. The view of the brain as a biological processor (and the processor as a digital brain) is well entrenched in popular culture. But the designs are fundamentally different.

Operationally, computers are precise, extremely fast and deterministic; brains are imprecise, slow, and non-deterministic. And, of course the underlying architectures are completely different. Computers relying on digital electronics, while the brain employs a complex mix of biomolecular structures and processes.

The SpiNNaker design meets the architecture of the brain halfway by going for lots of simple, low-power computing units, in this case, ARM968 processors. The initial Manchester-designed SpiNNaker multi-processor is a custom SoC with 18 of these processors integrated on-chip. (The original spec called for 20 processors per chip.) The multi-processor also incorporates a local bus, called Network-on-Chip or NoC, which links up the individual processors and off-chip memory. Each SpiNNaker node is reported to draw less than one watt of power, while delivering the computational throughput of a typical PC.

The design is purpose-built to simulate the action of spiking neurons. Spiking in this context means when neurons are stimulated above a certain threshold level to generate an event that can be propagated across a neural net. But instead of using neurotransmitters to do this, the computer is just passing data packets around.

To be truly useful, the spiking needs to happen in real-time. Fortunately, this is where computer technology shines. Electrical communication is actually more efficient than the biochemical version, so nothing exotic needs to be done in the hardware to make all this magical neural spiking a virtual reality.

And that may happen soon. The design phase of the project is coming to a close and the SpiNNaker team is starting to gather the pieces together. According to a news release this week, SpiNNaker chips were delivered in June (from Taiwan -- presumable TSMC), and have passed their functionality tests. The plan is to build a 50,000-node machine with up to one million ARM processors.

While that seems like a lot, researchers estimate that it will only be enough to represent about one percent of the real deal. A human brain contains around 100 billion neurons along with 1,000 million connections and a single ARM processor in the SpiNNaker chip can only handle 1,000 neurons. The good news is that one percent may be enough to answer a lot of questions about the functional operation of the brain.

Even at one percent, the scale of the machine is probably the trickiest part of the project. With so many processors in the mix, there are bound to be individual failures at fairly regular intervals. To deal with the inevitable, the designers made SpiNNaker fault tolerant at multiple levels. For example, each of the ARM processors can be disabled if they fail at start-up and a chip can remain functional even if "several processors fail." If an entire chip goes south, data can be rerouted to neighboring chips thanks to redundant inter-chip links.

The other challenge to scaling out is power, but here is where the ARM architecture pays dividends. The initial system of 50,000 nodes is estimated to draw just 23 KW to 36 KW of power. By supercomputing standards, that's just a pittance.  Of course, judged against the 20 watt version in our heads, SpiNNaker has a ways to go.

The power profile suggests that if there are no inherent scaling limitations in the hardware or software, the design could conceivably be used to build a machine that would support a "complete" human brain simulation for just a few megawatts. With improved process technology, that could easily slip into the sub-megawatt level.

For all that, SpiNNaker isn't designed to simulate higher level cognitive features -- the most interesting function of the brain. Inevitably that will require more complex hardware and software. So even if someone builds a super-sized SpiNNaker, it won't come close to the functionality of the 100 percent organic version anytime soon.

Posted by Michael Feldman - July 07, 2011 @ 7:40 PM, Pacific Daylight Time

Michael Feldman

Michael Feldman

Michael Feldman is the editor of HPCwire.

More Michael Feldman


Recent Comments

No Recent Blog Comments

Feature Articles

My Supercomputer is Bigger Than Yours!

Contributing commentator, Andrew Jones, offers a break in the news cycle with an assessment of what the national "size matters" contest means for the U.S. and other nations...
Read more...

Alternatives Emerge as Linpack Loses Ground

Today at the International Supercomputing Conference in Leipzing, Germany, Jack Dongarra presented on a proposed benchmark that could carry a bit more weight than its older Linpack companion. The high performance conjugate gradient (HPCG) concept takes into account new architectures for new applications, while shedding the floating point....
Read more...

Intel Snaps New Grips to HPC Hook

Not content to let the Tianhe-2 announcement ride alone, Intel rolled out a series of announcements around its Knights Corner and Xeon Phi products--all of which are aimed at adding some options and variety for a wider base of potential users across the HPC spectrum. Today at the International Supercomputing Conference, the company's Raj....
Read more...

Short Takes

Developers Tout GPI Model for Exascale Computing

Jun 19, 2013 | Supercomputer architectures have evolved considerably over the last 20 years, particularly in the number of processors that are linked together. One aspect of HPC architecture that hasn't changed is the MPI programming model.
Read more...

Supercomputers: Not Always the Best for Big Data

Jun 18, 2013 | The world's largest supercomputers, like Tianhe-2, are great at traditional, compute-intensive HPC workloads, such as simulating atomic decay or modeling tornados. But data-intensive applications--such as mining big data sets for connections--is a different sort of workload, and runs best on a different sort of computer.
Read more...

Gordon Flashes Its Versatility in HPC Workloads

Jun 18, 2013 | Researchers are finding innovative uses for Gordon, the 285 teraflop supercomputer housed at the San Diego Supercomputer Center (SDSC) that has a unique Flash-based storage system. Since going online, researchers have put the incredibly fast I/O to use on a wide variety of workloads, ranging from chemistry to political science.
Read more...

Supercomputers: Still the King of the HPC Hill

Jun 17, 2013 | The advent of low-power mobile processors and cloud delivery models is changing the economics of computing. But just as an economy car is good at different things than a full size truck, an HPC workload still has certain computing demands that neither the fastest smartphone nor the most elastic cloud cluster can fulfill.
Read more...

TACC Longhorn Takes On Natural Language Processing

Jun 14, 2013 | For all the progress we've made in IT over the last 50 years, there's one area of life that has steadfastly eluded the grasp of computers: understanding human language. Now, researchers at the Texas Advanced Computing Center (TACC) are utilizing a Hadoop cluster on its Longhorn supercomputer to move the state of the art of language processing a little bit further.
Read more...

Sponsored Whitepapers

Best Practices in Big Data Storage

05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.

Progress in Parallel: the Bull Parallel Programming Center

04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.

Sponsored Multimedia

HPCwire Live! Atlanta's Big Data Kick Off Week Meets HPC

Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?

Webinar: Mellanox Virtual Modular Switch, the Most Efficient 40GbE Aggregation Switch Solution

Join our webinar to learn how IT managers can migrate to a more resilient, flexible and scalable solution that grows with the data center. Mellanox VMS is future-proof, efficient and brings significant CAPEX and OPEX savings. The VMS is available today.

Blogs by Topics

Blogs by Author

HPC Blogroll


Featured Events






  • November 17, 2013 - November 22, 2013
    SC'13
    Denver, CO
    United States


HPCwire Events