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September 22, 2011
The Texas Advanced Computing Center (TACC) has revealed plans to deploy a cutting-edge petascale supercomputer courtesy of a $27.5 million dollar NSF award. Built by Dell, the system will consist of 2 petaflops of Sandy Bridge-EP processors with an 8 petaflop boost from Intel's Many Integrated Core (MIC) coprocessors. The machine is scheduled to boot up in late 2012 and be ready for production in January 2013.
Not only is this Dell's first petascale system -- at least the first one announced publicly -- it will likely be the first deployment of Intel's commercial MIC technology. In this case, the chips in question are pre-production versions of Knights Corner, the first commercial part in that product line. These early chips will be identical to the future production parts.
Stampede, as the system will be called, is meant to serve both traditional number crunching HPC applications and data-driven analytics applications within NSF's eXtreme Digital (XD) user community. XD includes the Extreme Science and Engineering Discovery Environment (XSEDE) project, the sucessor to TeraGrid that encompasses more than a dozen universities and two research labs. At 10 teraflops, Stampede will be the most powerful resource for XD users.
According to Jay Boisseau, TACC Director and PI of the Stampede project, the system is expected to have several hundred projects running on it from day one. "We want to bring in users with big data sets that are doing large-scale analyses, as well as the simulations types of users," he told HPCwire.
Data-intensive science applications include traditional ones like bioinformatics, but also codes from geosciences and astronomy -- application domains that are already accumulating large amounts of digital data. Boisseau thinks as much as half of Stampede's resources will be devoted to these types of applications.
The data-intensive support will bring in a new set of users, many of which are not as HPC savvy as the traditional simulations folks. For that, Boisseau is planning to develop a much richer software environment for this group, including new application portals and gateways, as was begun under the TeraGrid project. In addition, they will also look to bring in experts in statistics, data mining, data management, and so on, in order to support the data-driven application domain.
Some of the expertise and software resources are already built into the project via university collaborations. Besides The University of Texas at Austin, partner schools include Clemson University, University of Colorado at Boulder, Cornell University, Indiana University, Ohio State University, and The University of Texas at El Paso.
Hardware-wise, the foundation of Stampede is a 2 petaflop cluster with 6,400 x86 compute nodes, lashed together with FDR (56 Gbps) InfiniBand from Mellanox. Each node will house two of Intel's 8-core Xeon E5 (aka Sandy Bridge-EP) and 32 GB of DRAM.
Stampede will also include 16 big memory nodes, each sporting 1 terabyte of DRAM and 2 NVIDIA GPUs. Memory-wise, that's not exactly in SGI Altix UV territory, but it's a respectable capacity for extra-large SMP applications. Boisseau says they're also considering ScaleMP's virtual SMP solution to construct a shared memory environment across all 16 TB. The shared memory sub-cluster is slated to be used for some of the big data analytics applications that Stampede will host.
The cluster will also be hooked up to to Lustre storage nodes, also suppled by Dell. It will consist of 14 PB of disk, and deliver an aggregated bandwidth of 150 GB/second. "Over the lifetime of the project we're expecting that to grow substantially both in capacity and bandwidth over the lifetime of the system," said Boisseau.
The Dell system was developed by its Data Center Solutions division, under the code-name Zeus. Although the technology will debut in Stampede, the company is expecting to make the Zeus product generally available for "hyperscale" supercomputing in 2012.
Stampede's base cluster and storage nodes represent the lion's share of the NSF funding at $25 million. The remaining $2.5 million will go toward 8 petaflops worth of MIC coprocessors, which will be hooked into the x86 nodes via PCIe 3.0 links. MIC is Intel's x86-based manycore HPC architecture aimed at highly parallel codes, and competes head on with NVIDIA's Tesla and AMD's Firestream GPUS.
GPGPU enthusiasts were not completely slighted though. Besides the GPUs in the shared memory nodes, 128 of the 6,400 regular nodes will be outfitted with NVIDIA's next-generation Kepler GPUs to support remote visualization. Kepler is the successor to Fermi, NVIDIA's current GPU architecture. Tesla implementations of Kepler aimed at HPC servers should begin shipping sometime in 2012.
Intel has not announced an official launch date for the Knights Corner MIC product, but it should be generally available sometime in 2013, or perhaps late 2012 if Intel's 22nm process technology ramps up more quickly. The actual number of MICs in Stampede is not public, but Intel has promised them enough to deliver 8 peak petaflops.
Using a little quick math, each MIC chip will probably need to deliver at least 1.3 to 1.5 double precision teraflops to hit the 8 petaflop performance target. Coincidentally, the NVIDIA's Kepler GPU is also expected to deliver about 1.3 to 1.5 double precision teraflops. Note that the first MIC parts will be implemented with Intel's Tri-Gate 22nm technology, while the Kepler GPUs will be manufactured on standard 28nm technology.
At this point, Boisseau is expecting to receive all the Intel MIC coprocessors sometime this fall, possibly in time for a Linpack run at the November's TOP500. By that time, all the Sandy Bridge compute nodes should be fully deployed. If all goes according to plan, early access users should be able to start running codes on the machine by December 2012.
Although MIC will support a number of parallel computing models, the most straightforward one is OpenMP. This will be especially advantageous for users with hybrid MPI-OpenMP codes. The idea would be to just offload the OpenMP chunks to the coprocessors in order to parallelize those loops. Users with straight MPI codes will need to do more work to tap into MIC acceleration.
There is already an upgraded version of Stampede on the drawing board. About two years into the project, TACC is planning to deploy the second generation MIC coprocessors, with another (smaller) batch of chips. The goal is to add 5 more petaflops to the system, bringing its grand total to 15 peak petaflops sometime around the middle of the decade.
The NSF is will be funding Stampede for at least four years. Besides the inital $27.5 million outlay to build and install the system, an additional $24 million or so for system operation and support is expected to be on the table soon, bringing the total Stampede investment to more than $50 million. The project also includes an option for renewal in 2017, which would result in the deployment of an even larger and more powerful machine toward the end of the decade.
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