HPCwire: Xilinx Announces FPGA Design Suite for Floating Point Math

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November 01, 2011

Xilinx Announces FPGA Design Suite for Floating Point Math

New bit and cycle accurate, single, double and full custom precision floating-point now available in System Generator for DSP

SAN JOSE, Calif., Nov. 1 -- Xilinx, Inc. /quotes/zigman/80149/quotes/nls/xlnx XLNX -1.64% today announced the availability of ISE Design Suite 13.3 featuring new capabilities for DSP designers to easily implement bit-accurate single, double and full custom precision floating-point math operations in their designs targeting wireless, medical, aerospace and defense, high-performance computing and video applications. This flow is available through System Generator for DSP and leverages the Xilinx Floating-Point Operator IP LogiCORE. The combination of single, double and the industry's only full custom precision floating-point with the award winning productivity of System Generator for DSP, provides DSP designers a powerful environment to easily create, simulate and implement floating-point designs, as well as have more control over the silicon area and power required by their systems.

"Compared to competing solutions, only System Generator for DSP provides developers with a bit accurate solution, meaning we can guarantee that the simulation model will match the hardware implementation," said Tom Feist, Sr. Marketing Director, Design Methodology Marketing at Xilinx. "Xilinx 7 series 28nm FPGAs can deliver up to 1.33 teraflops of single-precision floating-point performance on one device, which is driving the demand for an easy-to-use design flow that delivers hand crafted results."

The Xilinx Floating-Point Operator core allows a range of floating-point arithmetic operations that can be performed in an FPGA. The operation is specified when the core is generated through the CORE Generator tool and now System Generator, and each operation variant has a common AXI-4 streaming interface. Previously, it was possible to implement a floating-point design in a Xilinx FPGA leveraging the full custom precision floating-point IP available in CORE Generator. However, the design flow required an understanding of VHDL or Verilog and simulation could be challenging for DSP developers. With the availability of ISE Design Suite 13.3, designers can now realize their systems from a higher level of abstraction and by leveraging the simulation capabilities in The MathWorks' Simulink tool enable the confidence that their design meets their fidelity requirements.

ISE Design Suite 13.3 also adds Red Hat Enterprise Linux 6 and provides productivity enhancements for Logic, Embedded and System Edition users. All editions contain enhancements to Plug-and-Play IP and device support for 7 series devices. Embedded and System Editions contain significant Platform Studio ease-of-use enhancements including a new Graphical Design View. Logic Edition contains productivity enhancement to the PlanAhead design analysis tool, including a graphical hierarchy viewer for HDL files.

Customers can get started today by downloading ISE Design Suite13.3. They can learn more about how IDS 13.3 can improve productivity by downloading Xilinx's latest whitepaper on floating-point support in System Generator (See Floating Point DSP Algorithms), as well as watch a new YouTube video on floating-point support.

Availability

ISE Design Suite 13 is immediately available for all ISE Editions and list priced starting at $2,995 for the Logic Edition and now supports 32 and 64 bit Windows 7. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site. To get started today with the ISE Design Suite 13 software release or for more information about the power and cost-saving design methodologies and productivity innovations introduced in ISE Design Suite 13, visit: www.xilinx.com/ISE .

About Xilinx

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit http://www.xilinx.com/ .

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Source: Xilinx, Inc.

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