Visit additional Tabor Communication Publications
November 09, 2011
Today's largest HPC systems are dominated (492 of the Top 500) by processors using two instruction sets (x86, Power) from three vendors (Intel, AMD, IBM). These processors have been typically designed for the highest single thread performance, but suffer from high cost (several hundred dollars to over $1500) and power demand (around 60-100W). As we build even larger and higher performance systems moving towards exascale, we might explore other avenues for delivering cost-efficient compute performance and reducing the power consumed by these systems.
In particular, there are at least three good reasons to explore whether processors designed for mobile systems can play a role in HPC, which I call innovation, federation and customization. Innovation, because the future of computing innovation is not on the desktop or in servers, but in ubiquitous computing, the internet of things. Federation, because embedded processors, like ARM-architecture devices, are available from a variety of vendors, thus freeing customers from single suppliers, allowing outstanding price and feature competition and increased innovation and flexibility. Customization, because the mobile market thrives on various manifestations of customization, and we in HPC might be able to take advantage of that.
Here, we use ARM-architecture processors as representative of mobile system processors, if only because ARM so dominates that space, though other possible processors include x86 (Intel Atom and AMD Geode), IBM PowerPC, MIPS, even embedded SPARC.
Innovation in the Post-PC World
In 2007, Steve Jobs predicted an upcoming explosion of "post-PC devices," using the iPod as an example. He didn't mean to suggest that the PC was dying or was doomed to eventual extinction, any more than PCs killed off workstations or mainframes. He meant that the growth seen in the PC industry was unlikely to continue at the same pace, and, as we've seen recently, the new growth path has been moving to phones, tablets, and other mobile, untethered, networked devices. This means that the innovators which have driven the PC world to ever greater capabilities have been moving to these new post-PC devices and ubiquitous computing. Hardware innovation is tending towards smaller, lower power devices.
Why do we care? Historically, supercomputers have been built with the devices available at the time. The first Cray-1 used four types of semiconductor chips: two types of NOR gates (fast for logic, bigger but slower for memory fanout), and two types of static RAM (fast for registers, slower but bigger for memory), and lots of wire. Contemporary supercomputers were built with essentially mainframe technology, mostly by the mainframe manufacturers.
A number of research parallel processors were designed, built and productively used in the 1980s using essentially workstation technology: printed circuit boards usually populated with commodity processors and connected by a high speed network. By the mid-1990s, massively parallel processors using RISC chips dominated the Top 500 supercomputer list.
In 2000, Intel introduced the Pentium 4, adding the double precision vector SSE2 instructions to the x86 family. This made the x86 a viable candidate for real supercomputing. Given the cost advantages of using high volume parts, more parallel supercomputers were designed using Intel and AMD processors. Within four years, over half the Top 500 supercomputers used some flavor of x86 processors, and that number is now close to 90%.
The cost of developing viable processors customized for general-purpose HPC is prohibitive, requiring system architects to use the best available commodity processors. Perhaps the one exception to that rule is IBM, which designed a special PowerPC chip for Blue Gene, though they adapted an existing commodity embedded processor rather than building a bespoke processor. When commodity innovation moves to the mobile world, we in the HPC industry may have to look at mobile processors as potentially the most cost effective solutions to our compute problems.
The Federation vs. the Empire
ARM, Ltd. doesn't actually produce and sell chips. ARM licenses the core IP to vendors who include ARM cores in their own products. Most of these designs are Systems-on-chip (SOCs), including much of the glue logic on the same chip as the processor, as well as application-specific logic. This makes for better integration and lower part count for the eventual customer.
An SOC for a cell phone might include a DSP or two for audio encode/decode, a graphics driver for the display, interface for the keyboard, and radio components in addition to the main processor. An SOC for automotive electronic stability control might have interfaces for wheel speed sensors, accelerometers, an interface to control the brakes, and perhaps even a temperature sensor.
ARM processor deliveries are far ahead of x86 and PowerPC processor deliveries each year in units. The architecture is solid and viable. Moreover, there are a number of chip vendors building and supplying parts with ARM architecture cores, giving customers a broad choice of supplier. No one vendor can control availability or price, and there's no fear of depending on a single source that may choose to change direction or that may not survive the long term. The ARM architecture may be the only viable candidate for an alternative processor to x86 and Power.
In the mobile world, standardization on ARM cores as the control processor has produced the same benefits that standardization on x86 has given the desktop. There are many choices for software ranging from operating systems, tools and applications ready to use for ARM processors. There is an army of trained programmers comfortable with programming, optimizing and tuning for ARM processors. There are a plethora of hardware devices that have been designed to work with ARM processors, though most of these would be integrated on the SOC.
There are two types of ARM licensees. Most vendors take the ARM core IP and integrate it directly into their own products; such an ARM core will be instruction-set compatible regardless of the vendor. Some vendors acquire an ARM architecture license, allowing them to augment their own ARM implementations. This gives them additional freedom to innovate or add extensions for particular target markets.
Customization for HPC
Within the ARM world, there is a high level of architectural variety. Among the more than 250 ARM microcontrollers in its catalog, STMicroelectronics, PGI's parent company, offers one 32-bit ARM microcontroller that draws about 10 milliamps when running at its full speed (32 MHz), and can be scaled to lower clocks and voltages to draw even less current.
The latest high end ARM Cortex-A15 design supports one to four cores, SIMD floating point, up to 4MB level 2 cache, and up to 1TB (40 bits) of memory address space. Note there are no Cortex A15 MCUs available yet, though several are in the works. This architectural variety is a real strength of ARM in the mobile market; a designer can choose a version with all the necessary features, and without any unnecessary baggage, and keep within a desired size or power envelope.
As specific examples, let's look at two current ARM processor offerings. One is the SPEAr chip from STMicroelectronics. The high end SPEAr 1340 has two ARM Cortex-A9 cores with up to 600MHz clock, 512KB level 2 cache, a Gigabit Ethernet port, a PCIe link, one SATA port, 2 USB ports, controllers for flash memory, interfaces for memory card, touch screen, small (6x6) keyboard, 7.1 channel sound, LCD controller, HD video decoders, digital video input, cryptographic accelerator, analog-digital converters, and various other IO features. The SPEAr is clearly designed for use in a multimedia device, and is optimized for low power.
The second is the ARMADA XP from Marvell; Marvell acquired the XScale business from Intel in 2006. The ARMADA XP is a relatively new product aimed directly at cloud computing. This chip has up to four ARM cores, up to 1.6GHz clock, 2MB shared level 2 cache, interface to DDR2 or DDR3 memory, four Gigabit Ethernet ports, four PCI-E ports, three USB 2.0 ports, two SATA ports, LCD controller, flash memory interface, UART, and more.
You could design either of those ARM chips right onto a small motherboard with memory and a disk and package a bunch of them into a 1U rack mount server. However, in the HPC space, do we really need USB ports, touch screen interfaces, and LCD controllers? Removing those from the chip might allow more room for more cores, or something more interesting.
The real potential for ARM architecture in HPC, and the third important reason to explore ARM, is the possibility to generate custom parts. Perhaps we could design the InfiniBand drivers right on the chip. Maybe we could add hardware support for quad-precision, which David Bailey and his colleagues predicted we'd want ten years or more ago. There may be an ability to add operations specific to certain markets, such as bioinformatics or financial.
Some of the more exciting systems over the past decade are custom designs, including Anton at D.E. Shaw Research, and the MDGRAPE-3 machine at RIKEN in Japan. In each case, custom design gives a significant performance advantage, but at high development cost, including fully custom software. Imagine if we could achieve similar performance advantages for specific applications, but retain most of the design and software development cost advantages of using standard chips.
In the mobile ARM space, there are different levels of customization. A fully custom chip would have a number of ARM cores, caches, memory interfaces, perhaps Ethernet or other ports, and maybe even some custom logic. The ARM architecture supports a coprocessor interface, so custom logic could be configured and controlled directly from software, just like early floating point units were. Even the ARM cores themselves can be customized by selecting a specific ARM version, or adding extensions like the NEON SIMD instructions.
The design of such a chip is easy on paper, but requires a long sequence of steps and perhaps a year or more before it comes out of fabrication and packaging. The design must be turned into RTL, laid out, verified, qualified on the technology to be used, a mask created, the chip fabricated and then tested. This takes both considerable time and money.
In the mobile space, the time and money is justified by very high volumes. Consider that Apple sold over 20 million iPhones and 9 million iPads in a single quarter this year. A custom chip in an iPhone or iPad would be justified based on that volume.
A second level is exemplified by the STMicroelectronics SPEAr chip mentioned above. ST offers these with a customizable logic block. During development, the customer would design and experiment with FPGA logic. When ready, the RTL from the FPGA is used to customize the on-chip logic. Because the chip is already designed with the custom logic block in place, validation is only required for the logic block, which takes only a few months.
A third level will be supported with the advent of through-silicon vias (TSVs). One obvious use for TSVs is to stack a memory chip on a processor chip, allowing lower latency, and higher bandwidth with many chip interconnections. But another important possibility is the ability to stack an FPGA or custom logic chip between a processor and memory, to be used like a coprocessor.
It's a good time to explore alternatives to current standard processors for HPC, for at least three reasons. First, the HPC market can't afford to develop its own processors, so it has to adopt the best of the commodity market, and the innovation in that market is moving to mobile. Second, ARM processors are by far the most popular 32-bit processors today and will soon have 64-bit versions available; moreover, there are many suppliers of ARM architecture processors, so if we're going to look for a viable alternative, ARM is the leading (perhaps the only) candidate. Third, the potential for customization either broadly for the HPC market, or narrowly for specific applications, could give significant benefits to HPC that we simply can't get from current commodity offerings. Add to these the potential cost and power advantages, and we'd be negligent if we don't study this now.
This doesn't mean that it's inevitable, or an easy decision. There are several challenges and missing pieces that need to be filled in along the way. That will be the topic of my next article.
About the Author
Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
May 08, 2013 |
For engineers looking to leverage high-performance computing, the accessibility of a cloud-based approach is a powerful draw, but there are costs that may not be readily apparent.
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.