November 14, 2011
New “lows” in high-performance computing: TI’s TMS320C66x multicore DSPs combine ultra-low power with unmatched performance, offering HPC developers the industry’s most power efficient solutions
Complete suite of software, tools and low cost development platform, enables easier development of high performance computing products on TI’s multicore DSPs
SEATTLE, Wash., Nov. 14 -- Shedding light on a new paradigm in high performance computing (HPC), Texas Instruments Incorporated (TI) (NYSE: TXN) is offering developers the industry's highest performing multicore digital signal processors (DSP) at the lowest power levels, based on its TMS320C66x DSP generation. TI's TMS320C6678 and TMS320TCI6609 multicore DSPs are well suited for computing applications in oil and gas exploration, financial modeling and molecular dynamics, where ultra-high performance, low power and easy programmability are critical requirements. TI provides free optimized libraries for HPC that make it easier to achieve maximum performance without spending time optimizing code, and supports standard programming languages such as C and OpenMP so developers can easily migrate their applications to take advantage of the power savings and performance.
"TI's new family of multicore DSPs deliver outstanding flops per watt performance and an exceptional level of density and integration," commented Phillip J. Mucci, founder and director of business development, Samara Technology Group. "This fact, combined with a number of options for high speed, low latency, socket to socket interconnect, makes TI's DSP an ideal building block for the high performance, high efficiency HPC systems of tomorrow."
Achieving maximum performance with multicore
With the highest performing floating point DSP core at 16 GFLOPs/W, TI's C66x KeyStone-based multicore DSPs are changing the way HPC developers meet requirements for performance, power efficiency and ease of use. Advantech, a global manufacturer of telecom computing blades and multicore processor platforms, has developed the DSPC-8681 multimedia processing engine (MPE), a half-length PCIe card with more than 500 GFLOPs of performance at an extreme low power consumption of 50W. In addition to the currently available PCIe card, TI and Advantech will soon have full length cards providing one and two teraflops of performance, transforming the industry with faster and more efficient solutions for HPC applications. TI's optimized math and imaging libraries, as well as standard programming model, make it easy for HPC developers to quickly achieve maximum performance.
"Since we released the DSPC-8681 earlier this year, it has gained early market adoption in compute intensive radar and medical imaging applications," said Eddie Lai, associate vice-president of business development, Advantech. "The launch of TI's latest suite of multicore development tools will significantly accelerate customer evaluation in HPC applications, and unleash the full potential of the C6678 multicore DSP in the supercomputing arena."
Meeting the needs of HPC developers – today and tomorrow
The DSPC-8681 PCIe card includes four C6678 multicore DSPs while the newer PCIe cards will include eight C6678 multicore DSPs to achieve one teraflop or four TCI6609 multicore DSPs to achieve two teraflops. The C6678 is the industry's highest performing multicore DSP in production today, featuring eight 1.25-GHz DSP cores, delivering 160 GFLOPs at 10W. TI's forthcoming TCIC6609 multicore DSP will offer developers 4X the performance of its C6678 multicore DSP, achieving 512 GFLOPs in just 32W, making DSPs an ideal solution for HPC and changing the way developers will choose solutions for applications. The TCIC6609, set to sample in 2012, is code compatible with the C6678 DSP, allowing developers to reuse their existing software and preserve their investment in TI multicore DSPs.
Easing multicore development
With its robust suite of multicore software, tools and low cost evaluation modules (EVMs), TI is easing development and getting developers closer to tapping the full performance of C66x multicore DSPs. Designers can begin development on the C6678 multicore DSP with the TMDSEVM6678L for $399. The EVM includes a free multicore software development kit (MCSDK), Code Composer Studio™ integrated development environment (IDE) and suite of application/demo codes to allow programmers to quickly come up to speed on the new platform.
About TI's KeyStone multicore architecture
Texas Instruments' KeyStone multicore architecture is the platform for true multicore innovation, offering developers a robust portfolio of high performance, low-power multicore devices. Unleashing breakthrough performance, the KeyStone architecture is the foundation upon which TI's new TMS320C66x DSP generation was developed. KeyStone differs from any other multicore architecture as it has the capacity to provide full processing capability to every core in a multicore device. KeyStone-based devices are optimized for high performance markets including wireless base stations, mission critical, test and automation, medical imaging and high performance computing. Learn more at www.ti.com/c66multicore.
Visit TI @ SC11
While at SC11, visit TI, in booth #4200 to view the latest multicore solutions and demos for ultra-low power, super high performance computing applications.
For more information:
About Texas Instruments
Texas Instruments semiconductor innovations help 80,000 customers unlock the possibilities of the world as it could be – smarter, safer, greener, healthier and more fun. Our commitment to building a better future is ingrained in everything we do – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. This is just the beginning of our story. Learn more at www.ti.com.
-----
Source: Texas Instruments
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Read more...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
Read more...
Supercomputing veteran, Bo Ewald, has been neck-deep in bleeding edge system development since his twelve-year stint at Cray Research back in the mid-1980s, which was followed by his tenure at large organizations like SGI and startups, including Scale Eight Corporation and Linux Networx. He has put his weight behind quantum company....
Read more...
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
Read more...
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
Read more...
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
Read more...
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
Read more...
May 08, 2013 |
For engineers looking to leverage high-performance computing, the accessibility of a cloud-based approach is a powerful draw, but there are costs that may not be readily apparent.
Read more...
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.