Nvidia
NetApp
HPCwire

Since 1986 - Covering the Fastest Computers
in the World and the People Who Run Them

Language Flags

Visit additional Tabor Communication Publications

Datanami
Digital Manufacturing Report
HPC in the Cloud
Green Computing Report

Tabor Communications
Corporate Video

Intel Xeon E5 Debuts on TOP500; First Intel MIC Co-processor Hits 1 Teraflop


  • Intel Xeon processor E5 family, world's first server chip to support the PCI Express* 3.0 I/O integration, debuts on TOP500 list, powering 10 supercomputers.
  • Intel's "Knights Corner" product, the first commercial co-processor based on the Intel Many Integrated Core (Intel MIC) architecture, was shown for the first time breaking the barrier of 1 TFLOPS double precision performance.
  • Intel announced additional investments and new partner projects with R&D laboratories to pursue the goal of achieving Exascale performance by 2018.
  • Intel processors power 85 percent of all new entries to the latest TOP500 list of supercomputers, with Intel Xeon processor 5600 series being most popular selected for 223 systems.

SEATTLE, Nov. 15 -- At SC11, Intel Corporation revealed details about the company's next-generation Intel Xeon processor-based and Intel Many Integrated Core (Intel MIC)-based platforms designed for high-performance computing (HPC). The company also outlined new investments in research and development that will lead the industry to exascale performance by 2018.

During his briefing at the conference, Rajeeb Hazra, general manager of Technical Computing, Intel Datacenter and Connected Systems Group, said that the Intel Xeon processor E5 family is the world's first server processor to support full integration of the PCI Express 3.0 specification. PCIe 3.0 is estimated** to double the interconnect bandwidth over the PCIe* 2.0 specification while enabling lower power and higher density server implementations. New fabric controllers taking advantage of the PCI Express 3.0 specification will allow more efficient scaling of performance and data transfer with the growing number of nodes in HPC supercomputers.

The early-performance benchmarks revealed that the Intel Xeon E5 delivers up to 2.1 times more performance in raw FLOPS (Floating Point Operations Per Second as measured by Linpack) and up to 70 percent more performance using real-HPC workloads compared to the previous generation of Intel Xeon 5600 series processors.

"Customer acceptance of the Intel Xeon E5 processor  has exceeded our expectations and is driving the fastest debut on the TOP500 list of any processor in Intel's history," said Hazra. "Collecting, analyzing and sharing large amounts of information is critical to today's science activities and requires new levels of processor performance and technologies designed precisely for this purpose."

The Intel Xeon E5 processors made their way onto the TOP500 list in the year of the 40th anniversary of availability of the world's first microprocessor (the Intel 4004 processor) and on the 10th anniversary of the launch of the Intel Xeon brand. Since the introduction of Intel Xeon processors in 2001, Intel estimates that Xeon processor performance has increased by more than 130 times***.

Two months since its initial shipments to supercomputer centers, Intel Xeon E5 processors now power 10 systems on the TOP500 list. More than 20,000 of these processors are in operation, delivering a cumulative peak performance of more than 3.4 Petaflops.

As previously announced, the upcoming Intel Xeon processor E5 family will power several other future supercomputers, including the 10 PFLOPS "Stampede" at Texas Advanced Computing Center, the 1.6 PFLOPs "Yellowstone" at The National Center for Atmospheric Research, the 1.6 PFLOPS "Curie" at GENCI, the 1.3 PFLOPS system at International Fusion Energy Research Center (IFERC) and more than 1 PFLOPS "Pleiades" expansion at NASA.

Intel started shipping the Intel Xeon processor E5 family to a small number of cloud and HPC customers in September, with broad availability planned in the first half of 2012. Intel is tracking more than 400 design wins for the Intel Xeon processor E5 family, nearly double the amount at time of launch of the Xeon 5500/5600 generation. Demand for initial production units is approximately 20 times greater than for previous generations of the Intel Xeon 5500 or 5600 series processors.

During SC11 Intel also provided details on its greatly expanded lineup of server boards and chassis, including products specifically optimized for HPC, which will be ready to support the launch of the Intel Xeon Processor E5.

First Teraflops Intel Many Integrated Core Co-Processor Showcased

Intel also reiterated its commitment to delivering the most efficient and programming-friendly platform for highly parallel applications. The benefits of the Intel MIC architecture in weather modelling, tomography, proteins folding and advanced materials simulation were shown at Intel's booth at SC'11.

The first presentation of the first silicon of "Knights Corner" co-processor showed that Intel architecture is capable of delivering more than 1 TFLOPs of double precision floating point performance (as measured by the Double-precision, General Matrix-Matrix multiplication benchmark -- DGEMM*). This was the first demonstration of a single processing chip capable of achieving such a performance level.

"Intel first demonstrated a Teraflop supercomputer utilizing 9,680 Intel Pentium Pro Processors in 1997 as part of Sandia Lab's "ASCI RED" system," Hazra said. "Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history."

"Knights Corner," the first commercial Intel MIC architecture product, will be manufactured using Intel's latest 3-D Tri-Gate 22nm transistor process and will feature more than 50 cores. When available, Intel MIC products will offer both high performance from an architecture specifically designed to process highly parallel workloads, and compatibility with existing x86 programming model and tools.

Hazra said that the "Knights Corner" co-processor is very unique as, unlike traditional accelerators, it is fully accessible and programmable like fully functional HPC compute node, visible to applications as though it was a computer that runs its own Linux*-based operating system independent of the host OS.

One of the benefits of Intel MIC architecture is the ability to run existing applications without the need to port the code to a new programming environment. This will allow scientists to use both CPU and co-processor performance simultaneously with existing x86 based applications, dramatically saving time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary languages.

Intel Increases Investment in Exascale Computing Labs

As previously announced at the International Supercomputing Conference 2011 in Hamburg, Germany, Intel's goal is to deliver Exascale-level performance by 2018 (which is more than 100 times faster performance than is currently available) while only requiring two times the power usage of the current top supercomputer. Fundamental to achieving that goal is working closely with the HPC community, and today Hazra announced several new initiatives that will help to achieve that goal.

Intel and the Barcelona Supercomputing Center (BSC) have signed a multi-year agreement to create the Exascale Laboratory in Barcelona, Intel's fourth European Exascale R&D lab that joins existing sites in Paris, Juelich (Germany) and Lueven (Belgium). This new laboratory will focus on scalability issues in the programming and runtime systems of Exascale supercomputers.

Additionally, the Science and Technology Facilities Council (STFC) and Intel have signed a memorandum of understanding to develop and test technology that will be required to power the supercomputers of tomorrow. Under this initial agreement, STFC's computational scientists at its Daresbury Laboratory in England and Intel will work together to test and evaluate Intel's current and future hardware with leading software applications to ensure that scientists are ready to exploit Intel's supercomputer systems of the future.

TOP500 Supercomputers

The 38th edition of the TOP500 list, which was announced at SC11, shows that the world's leading scientists and institutions continue to base their supercomputers on Intel Xeon processors. Out of all new entries to the list compared to last edition, Intel-powered supercomputers accounted for close to 85 percent. The Intel Xeon 5600 series processor is the top processor on the list, powering 223 systems. Intel Xeon processor E5 family made its introduction in 10 systems on the list with record-breaking 152 GFLOPS per socket and 91 percent efficiency. Intel processors also power five systems in the top 10 and almost 77 percent of all listed supercomputers. The complete report is available at www.top500.org.

About Intel

Intel (NASDAQ: INTC) is a world leader in computing innovation. The company designs and builds the essential technologies that serve as the foundation for the world's computing devices. Additional information about Intel is available at newsroom.intel.com and blogs.intel.com.

-----

Source: Intel Corp.

Sponsored Links

Accelerate your science with Seneca
One of the first HPC providers installing a 4X NVIDIA Kepler K-20 cluster. Invites you to a free evaluation on Seneca’s NVIDIA K20 Kepler cluster, pre-loaded with AMBER, NAMD, LAMMPS

High-Performance Computing in Action
Businesses that want to be on the cutting edge of their industries are increasingly turning to high-performance computing (HPC) solutions to handle complex compute processes and speed up their rate of innovation. Download this Executive Brief to see how businesses in energy, life sciences and entertainment put HPC solutions to work in their operations.

Webinar: Programming Heterogeneous X64+GPU Systems Using OpenACC
Join Michael Wolfe as he compares the advantages and costs of using both low-level models and the directive-based OpenACC model for programming accelerated heterogeneous systems. Registration is free.

May 22, 2013

May 21, 2013

May 20, 2013

May 17, 2013

May 16, 2013

May 15, 2013

May 14, 2013

May 13, 2013

May 10, 2013

May 09, 2013


Most Read Features

Most Read Around the Web

Most Read This Just In


Feature Articles

NSF Forges Further Beyond FLOPs

In a recent solicitation, the NSF laid out needs for furthering its scientific and engineering infrastructure with new tools to go beyond top performance, Having already delivered systems like Stampede and Blue Waters, they're turning an eye to solving data-intensive challenges. We spoke with the agency's Irene Qualters and Barry Schneider about..
Read more...

CERN, Google Drive Future of Global Science Initiatives

Large-scale, worldwide scientific initiatives rely on some cloud-based system to both coordinate efforts and manage computational efforts at peak times that cannot be contained within the combined in-house HPC resources. Last week at Google I/O, Brookhaven National Lab’s Sergey Panitkin discussed the role of the Google Compute Engine in providing computational support to ATLAS, a detector of high-energy particles at the Large Hadron Collider (LHC).
Read more...

Saddling Phi for TACC’s Stampede

The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Read more...

Short Takes

Building Supercomputers with Raspberries

May 22, 2013 | At some point in the not-too-distant future, building powerful, miniature computing systems will be considered a hobby for high schoolers, just as robotics or even Lego-building are today. That could be made possible through recent advancements made with the Raspberry Pi computers.
Read more...

Running Computational Fluid Dynamics in the Cloud

May 16, 2013 | When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
Read more...

Computing the Physics of Bubbles

May 15, 2013 | Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
Read more...

Internet2 Awards Program Seeks Innovative Applications

May 10, 2013 | Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
Read more...

Floating Funding to Exascale Island

May 09, 2013 | The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
Read more...

Sponsored Whitepapers

Best Practices in Big Data Storage

05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.

Progress in Parallel: the Bull Parallel Programming Center

04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.

Sponsored Multimedia

SGI DMF ZeroWatt Disk Solution

In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.

Cray CS300-AC Cluster Supercomputer Air Cooling Technology Video

The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.

SC12 Editorial Feature HPCwire Soundbite sponsored by ISC Xyratex

HPC Job Bank


Featured Events


  • June 16, 2013 - June 20, 2013
    ISC'13
    Leipzig,
    Germany

  • June 17, 2013 - June 18, 2013
    Forecast 2013
    San Francisco, CA
    United States





HPCwire Events