CSCS Top Right Frontpage
HPCwire

Since 1986 - Covering the Fastest Computers
in the World and the People Who Run Them

Language Flags

Visit additional Tabor Communication Publications

Datanami
Digital Manufacturing Report
HPC in the Cloud
Green Computing Report

Tabor Communications
Corporate Video

NVIDIA Launches Kepler Into HPC


NVIDIA has introduced its first Kepler-generation GPU product for high performance computing, and revealed some of the inner working of the new architecture. The announcement took place at the kickoff of the company's GPU Technology Conference (GTC) taking place this week in San Jose, California.

Kepler's HPC debut comes at time when NVIDIA has established itself as the go-to chip vendor for heterogeneous supercomputing. With Intel's MIC product launch several months away and AMD still primarily focused on the consumer space with its CPU-GPU Fusion processors, NVIDIA has enjoyed free reign in the HPC acceleration business.

And it appears to be turning into quite a business. IDC is reporting that 75 percent of total HPC customer will use GPUs by 2014. And according to Sumit Gupta, NVIDIA's senior director of the Tesla GPU Computing business unit, by the end of this year, 50 to 60 percent of the top apps at the big supercomputing labs around the world will be accelerated by GPUs. That level of interest is also reflected in CUDA toolkit downloads, which Gupta reports is occurring at the rate of one every 60 seconds. "We're seeing a true liftoff in the number of application accelerated by GPUs," he says.

In 2010, NVIDIA changed the game in HPC with the Fermi chips, introducing error corrected memory and some serious double precision floating point performance -- 665 gigaflops, to be precise. Gupta believes the feature set they're bringing to the table with the Kepler architecture will provide the basis for same sort of technological discontinuity.

One of the more interesting pieces of the Kepler HPC technology is the so-called "Hyper-Q" capability. Essentially it allows the GPU to work on as many as 32 CPU-driven MPI tasks simultaneously. With Fermi, the GPU was only able to run a single MPI task at a time (although multiple tasks could be on-chip, waiting to be switched to). So if a task only happens to use a quarter of the cores, the remain three quarters of the GPU was idle. Now with up 32 tasks running concurrently, both the CPU host and the GPU accelerator should be better utilized, with less idle time all around.

Another notable Kepler enhancement is something the Nvidians call "dynamic parallelism." This allows the GPU to do a lot more processing independently of the CPU. The traditional model was for the CPU to send the GPU some work via a CUDA call; when it was done, the GPU would have to wait for more work from the host.

With dynamic parallelism, that kind of ping-pong processing can be greatly reduced. CUDA functions that previously would have been launched from the CPU, can now be called from the CUDA code itself on the GPU. Performance should be better since communication overhead between the two chips will be reduced. In essence, more of the application will end up on the GPU, allowing the CPU to free to do its own thing.

Perhaps more importantly, notes Gupta, is that this capability will allow developers to write applications for the GPU much more naturally, since much of the CPU-to-GPU calls can be done away with. And it will allow more complex and irregular types of applications (like adaptive mesh codes) to be ported more easily to the GPU. "This is a ground-breaking change," says Gupta.

But the fundamental upgrade to Kepler is its increased core count. To make that happen, the engineers did a complete redesign of the GPU's streaming multiprocessor (SM), the internal structure that provides thread processing. In Fermi, each SM contained 32 cores; while in Kepler, that's been bumped way up to 192.

Part of that was possible thanks to the smaller 28nm process technology for the Kepler silicon, but the engineers also freed up additional die real estate by compressing the control logic on the multiprocessor. The result is that each Kepler SM -- now referred to as SM extreme, or SMX -- has six times as many cores as its predecessor.

To go along with the extra parallelism, the NVIDIA engineers reduced the clock frequency those cores are running at by about half. In doing so, they were able to realize about three times the performance per watt of the Fermi GPU. If you're keeping score at home, that means a Kepler GPU that draws the same 225 watt TDP as the latest Fermi Tesla part should deliver just shy of 2 teraflops of double precision.

That product, however, will not be NVIDIA's first Kepler Tesla that it announced today at the GTC event. Known as the K10, this initial HPC Kepler offering will house two consumer-grade GK104 GPUs, the same chip used in the Kepler GeForce products that were introduced in March.

As such it lacks the nifty high-end Hyper-Q and dynamic parallelism features mentioned above. Plus it's rather underpowered in the double precision (DP) floating point department, managing only 190 gigaflops -- less than a third that of the Fermi Tesla M2090.

Where the K10 shines is in single precision (SP), delivering 4.48 teraflops across the two GPUs, which is three and a half times the SP floppery of the Fermi M2090 hardware. This makes it especially suitable for applications like image/signal processing, seismic codes, and maybe some mixed precision algorithms in academia. According to NVIDIA, initial testing with LAMMPS, NAMD, seismic processing, and certain integer-centric defense codes showed performance increases between 1.5X and 2.0X compared to the Fermi M2090. Petrobras, the Brazilian oil and gas company, reported a 1.8X speedup on its seismic application with the K10.

The new card is also plenty fast at data transfer speeds, sporting 320 GB/sec of memory bandwidth and a host connection of 16 GB/sec, courtesy of PCIe Gen 3. Memory capacity is a respectable 8 GB, which is shared between the two GPUs on the card.

The K10 is shipping this month and will be initially available in products from IBM, HP, Dell, SGI, Appro, and Supermicro.

Further down the road is the K20, which will represent NVIDIA's first true Kepler-generation supercomputing Tesla. The K20 will be based on the GK110 GPU, which is the one built for HPC duty. It will fold in the Hyper-Q and dynamic parallelism technology, and will be fully outfitted for double precision. For the time being, NVIDIA is keeping mum on the peak performance, but this is the chip that could be flirting with 2 DP teraflops. In any case, we'll have to wait until later in the year to get the actual specs.

The K20 will be the Tesla deployed in "Titan" supercomputer at Oak Ridge National Lab, and in the NCSA's "Blue Waters" system at the University of Illinois. Some of new chips could be installed in these top supers as early as the fall, but volume production of the K20 is slated for Q4.

Although the multi-petaflop systems mentioned above will get first crack at the K20, this is the product NVIDIA is hoping universities and mid-sized installations start adopting to build their own petaflop supers. Gupta says Kepler-equipped supers of this size will be able to fit into 10 server racks and draw a relatively modest 400 KW of power, well within the reach of a modest-sized organization. If Kepler indeed becomes the enabling technology of petascale supercomputing for the masses, NVIDIA will have delivered another GPU that, once again, changed the game in HPC.

June 19, 2013

June 18, 2013

June 17, 2013

June 14, 2013

June 13, 2013

June 12, 2013

June 11, 2013

June 10, 2013

June 07, 2013

June 06, 2013


Most Read Features

Most Read Around the Web

Most Read This Just In


Short Takes

Supercomputers: Not Always the Best for Big Data

Jun 18, 2013 | The world's largest supercomputers, like Tianhe-2, are great at traditional, compute-intensive HPC workloads, such as simulating atomic decay or modeling tornados. But data-intensive applications--such as mining big data sets for connections--is a different sort of workload, and runs best on a different sort of computer.
Read more...

Gordon Flashes Its Versatility in HPC Workloads

Jun 18, 2013 | Researchers are finding innovative uses for Gordon, the 285 teraflop supercomputer housed at the San Diego Supercomputer Center (SDSC) that has a unique Flash-based storage system. Since going online, researchers have put the incredibly fast I/O to use on a wide variety of workloads, ranging from chemistry to political science.
Read more...

Supercomputers: Still the King of the HPC Hill

Jun 17, 2013 | The advent of low-power mobile processors and cloud delivery models is changing the economics of computing. But just as an economy car is good at different things than a full size truck, an HPC workload still has certain computing demands that neither the fastest smartphone nor the most elastic cloud cluster can fulfill.
Read more...

TACC Longhorn Takes On Natural Language Processing

Jun 14, 2013 | For all the progress we've made in IT over the last 50 years, there's one area of life that has steadfastly eluded the grasp of computers: understanding human language. Now, researchers at the Texas Advanced Computing Center (TACC) are utilizing a Hadoop cluster on its Longhorn supercomputer to move the state of the art of language processing a little bit further.
Read more...

Titan Didn't Redo LINPACK for June Top 500 List

Jun 13, 2013 | Titan, the Cray XK7 at the Oak Ridge National Lab that debuted last fall as the fastest supercomputer in the world with 17.59 petaflops of sustained computing power, will rely on its previous LINPACK test for the upcoming edition of the Top 500 list.
Read more...

Sponsored Whitepapers

Best Practices in Big Data Storage

05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.

Progress in Parallel: the Bull Parallel Programming Center

04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.

Sponsored Multimedia

HPCwire Live! Atlanta's Big Data Kick Off Week Meets HPC

Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?

Webinar: Mellanox Virtual Modular Switch, the Most Efficient 40GbE Aggregation Switch Solution

Join our webinar to learn how IT managers can migrate to a more resilient, flexible and scalable solution that grows with the data center. Mellanox VMS is future-proof, efficient and brings significant CAPEX and OPEX savings. The VMS is available today.

Atlanta's Big Data Kick Off Week Meets HPC Cray Xyratex

HPC Job Bank


Featured Events






  • November 17, 2013 - November 22, 2013
    SC'13
    Denver, CO
    United States


HPCwire Events