Visit additional Tabor Communication Publications
July 12, 2012
Intel, AMD, NVIDIA, and Whamcloud have been awarded tens of millions of dollars by the US Department of Energy (DOE) to kick-start research and development required to build exascale supercomputers. The work will be performed under the FastForward program, a joint effort run by the DOE Office of Science and the National Nuclear Security Administration (NNSA) that will focus on developing future hardware and software technologies capable of supporting such machines.
The program is being contracted through Lawrence Livermore National Security, LLC as part of a multi-lab consortium that includes Argonne National Laboratory, Lawrence Berkeley National Laboratory, Lawrence Livermore National Laboratory, Los Alamos National Laboratory, Oak Ridge National Laboratory, Pacific Northwest National Laboratory, and Sandia National Laboratories.
Although we're only six to eight years away from the first exaflops systems, the DOE's primary exascale program has yet to be funded. (And since this is an election year in the US, such funding will probably not fall into place until 2013.) In the interim, FastForward was devised in order to begin the needed R&D for some of the exascale foundational technologies, in particular, processors, memory and storage.
At least some of the impetus for the program came from the vendors themselves. According to Mark Seager, Intel's CTO for the company's High Performance Computing Ecosystem group, the DOE was told by multiple commercial partners that research for the component pieces needed to get underway this year if they hoped to field an exascale machine by 2020. That led to the formation of the program, and apparently there was enough loose change rolling around at the Office of Science and NNSA to fund this more modest effort.
Although all the FastForward subcontracts have yet to be made public, as of today there are four known awards:
Although the work is not intended to fund the development of "near-term capabilities" that are already on vendors' existing product roadmaps, all of this work will be based upon ongoing R&D efforts at these companies. The DOE is fine with this since the commercialization of these technologies is really the only way these government agencies can be assured of cost-effective exascale machines. The FastForward statement of work makes a point of spelling out this arrangement, thusly: "While DOE’s extreme-scale computer requirements are a driving factor, these projects must also exhibit the potential for technology adoption by broader segments of the market outside of DOE supercomputer installations."
For example, Intel's FastForward processor work will be based on the company's MIC (Many Integrated Core) architecture, which the company is initially aiming at the supercomputing market, but with the intent to extend it into big data business applications and beyond. The first MIC product, under the Xeon Phi brand, is scheduled to be launched before the end of 2012, but this initial offering is at least a couple of generations away from supporting exascale-capable machines. According to Seager, a future processor of this kind will need much improved energy efficiency, a revamped memory interface, and higher resiliency.
Although the x86 ISA will be retained, this future MIC architecture will incorporate some "radical approaches" to bring the technology into the exascale realm. To begin with, says Seager, that means reducing its power draw two to three times greater than what would naturally be achieved with transistor shrinkage over the rest of the decade. "It's a daunting challenge to do better than what Moore's Law will give you," Seager told HPCwire.
Fortunately, he says, Intel will be able to leverage its near-threshold voltage circuitry research, some of which was funded under UHPC (Ubiquitous High Performance Computing), DARPA's now defunct exascale program. Shekhar Borkar, who was the PI for the UHPC work, along with Seager and former IBM'er Al Gara, will be heading up the FastForward work at Intel.
For the exascale memory subcontract, Intel will be leveraging its work with Micron Technology on the Hybrid Memory Cube. The idea is to use similar technology to incorporate 3D stacks of memory chips into the same package as the processor. In-package integration shortens the distance considerably between the processor and the memory, which significantly increases bandwidth and lowers latency. At the same time, cache management is going to be redesigned to optimize the power-performance of memory reads and writes.
Like Intel, AMD will be basing its FastForward processor research on a current design, in this case the company's APU (Accelerated Processing Unit) product line and the related Heterogeneous Systems Architecture (HSA) standard -- that according to Alan Lee, AMD's corporate vice president for Advanced Research and Development. The current crop of APUs, which integrate CPUs and GPUs on-chip, are aimed at consumer devices, such as laptops, netbooks, and other mobile gear. But AMD has designs on extending its heterogeneous portfolio into the server arena, and the DOE just gave them about 12 million more reasons to do so.
Since AMD first needs to transform their APU into a server design, the chipmaker has a somewhat different, and perhaps longer path to exascale than Intel, which is at least starting with server-ready silicon. On the other hand the MIC architecture is not heterogenous (and may never be), so AMD does have a certain advantage there. "That is the truly unique technology and the strongest one that AMD brings to bear -- that we have a world-class CPU and GPU brought together in a single APU," says Lee.
Lee was less forthcoming about the starting point for the memory research under the FastForward work, other than to say it would be optimizing the technology around its heterogeneous architecture and would involve high-speed interconnects as well as different types and arrangements of memory.
More than anything, Lee sees this R&D work as producing dividends in other areas of AMD's business. He says the fundamental technologies that the DOE wants for exascale are those the computer industry needs, not just in the future, but right now, referring to the big data domain, in particular. "I expect that a lot of the technology that you see us develop has the potential to make it into a variety of different server products of different genres," says Lee.
To counterbalance the Intel and AMD work, is NVIDIA, which will be using the company's Echelon design as the starting point for its FastForward work. Echelon, which was also funded under DARPA's UHPC program, is based on a future 20-teraflop microprocessor that integrates 128 streaming processors, 8 latency (CPU-type) processors, and 256MB of SRAM memory on-chip. The technology is in line to follow Maxwell, NVIDIA's GPU architecture scheduled to take the reigns from Kepler in a couple of years. Unlike the Intel and AMD efforts, NVIDIA's contract is for processor technology only, although the Echelon design also specified an exascale-capable memory subsystem.
While the DOE spread its bets around for the FastForward processor- and memory-based research, there was only one storage subcontract awarded. That went to Whamcloud, who in conjunction with EMC, Cray and HDF Group, got the nod to provide the R&D work for storage and I/O.
The work specifies bringing object storage into the exascale realm, and will be based on the Lustre parallel file system technology. As a result, any development in this area will be open sourced and be available to the Lustre community.
Although the FastForward contracts limit their scope to specific exascale components, rather than complete systems, the research won't be performed in a complete vacuum. The vendors are expected to work in conjunction with the DOE's exascale co-design centers, a group that encapsulates various proxy applications, algorithms, and programming models important to the agency. The idea is to align the vendor R&D designs with the DOE's application needs and expectations, the implication being that these are general enough to apply to a wide range of exascale codes both inside and outside the Energy Department.
All the FastForward contracts have a two-year lifetime, so are slated to expire in 2014. The follow-on DOE work to design and build entire exascale supercomputers are dependent on future budgets. Assuming the feds comes through with the funding, that effort is expected to cost hundreds of millions of dollars over the next several years.
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.