As Intel's Xeon Phi processor family gets ready to debut later this year, the chipmaker continues to reveal some of the details of its first manycore offering.  Although the company isn't yet ready to talk speeds and feeds, this week they did divulge some of their design decisions that they believe will make the Xeon Phi coprocessor shine as an HPC accelerator. The new revelations were presented on Tuesday at the IEEE-sponsored Hot Chips conference in Cupertino, California.

The Hot Chips presentation was manned by George Chrysos, chief architect of "Knights Corner," the code name for Intel's first Xeon Phi product.  This fall, new chip is scheduled to debut in supercomputers, most notably the 10-petaflop "Stampede" system at the Texas Advanced Computing Center.  Although Knights Corner silicon will act as a coprocessors to the Xeon CPUs in that system, they will represents 80 percent of the total flops.

HPCwire talked with Chrysos (before Hot Chips) to get a preview of what he'd be talking about.  In essence, Intel is divulging some of the architectural details of the core and interconnect design, but is not releasing core counts, processor frequency, or memory bandwidth. That information will be forthcoming at the official product launch, which is more than likely to occur during the Supercomputing Conference (SC12) in November.

The major design goal of the Knights Corner microarchitecture was to pack a lot of number-crunching capability into a very power-efficient package. They did this by gluing a big vector processor onto a bare-bones x86 core.  In fact, according to Chrysos, only two percent of the Knights Corner die is dedicated to decoding x86 instructions.  The majority of the silicon real estate is devoted to the L1 and L2 caches, the memory I/O, and of course, the vector unit.

With regard to the latter, the 512-bit vector unit is the largest ever developed by Intel. Each one can dispatch 8 double precision or 16 single precision SIMD operations (integer or floating point) per clock cycle.  That's twice as many as can be delivered by the latest x86 CPUs -- the Intel Xeon Sandy Bridge and AMD Bulldozer processors.  And since there will be 50-plus cores on Knights Corner, we're talking over 400 double precision flops per cycle. Even on a 2 GHz processor, that works out to 800 gigaflops. But since Intel is using its latest 22nm technology process, you know they're going to be much more aggressive than that.

It's more than just extra-wide vectors though  Chrysos says the design also incorporates other features optimized for HPC-type workloads.  In particular, they added a special math accelerator they call the Extended Map Unit (EMU), which does polynomial approximations of transcendent functions like square roots, reciprocals, exponents, and so.  The idea is to speed up execution of these functions in hardware.  According to Chrysos, it's the first EMU for an x86-based processor.

The Knights Corner vector unit also includes a scatter-gather capability, another first for the x86 line. Scatter-gather , which is sometime referred to as vector addressing or vector I/O, is a way to optimize storing and fetching of data from non-contiguous memory addresses. It's especially useful for processing sparse matrices, which is fundamental to many HPC applications.

As far as memory bandwidth, Chrysos didn't volunteer information in that regard, other than to say the memory subsystem on Knights Corner will be "very competitive." Multiple memory controllers will be sprinkled among the cores, and, in such a way as to optimize speed and latency.

Which bring us to the Knights Corner cache setup. Like traditional CPUs, the new chip will incorporate cache coherency in hardware, but in this case, extended to handle a manycore environment. On Knights Corner, L2 cache is 512 KB per core -- twice the size of those on the Sandy Bridge Xeons. On top of that they've added a translation lookaside buffer (TLB) to speed address translation, tag directories (TDs) to snoop across all of the cores' L2 caches, and a Dcache capability to simultaneously load and store 512 bits per clock cycle. Finally, Intel included a prefetch capability for the L2, to boost the performance when data is streaming from memory.

All of these capabilities are designed to keep the cores well fed with data, and, as much as possible, avoid the much larger amount of time and energy required to access main memory off the chip. According to Chrysos, based on the Spec FP 2006 benchmarks, these cache features in aggregate have increased per core performance by an average of 80 percent.

For CPU-type architectures, cache coherency is pretty much business as usual. This is quite different from the GPU, which relies less on caches and more on maximizing bandwidth for memory streaming and lots of cores to hide latency. Although the general-purpose GPUs, especially the latest from NVIDIA, have cache hierarchies, they are not globally coherent.

NVIDIA, though, does have a more flexible approach. For example, its L1 cache on Fermi, and now Kepler, is user configurable and can be split between L1 cache and scratchpad memory. The L2 cache is just shared across all the streaming multiprocessors, which are roughly analogous to CPU cores. If coherency is to be maintained on the GPU it must be done in software.

Intel believes it has a "fundamental advantage" in its hardware-based cache coherency, since not only does it minimize the more expensive memory I/O, but it is also easier to program. Along those same lines, Intel will continue to promote x86 programmability as a big advantage of Knights Corner compared to the more specialized CUDA- or OpenCL-based approaches of GPUs. All of this is about to tested on the HPC battlefield later this year. Stay tuned.

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