October 22, 2012
Rogue Wave Software recently announced upcoming support for the Intel Xeon Phi coprocessor in four of its leading software products. Scott Lasica, VP of Products and Alliances, answered questions about this strategic announcement and Rogue Wave’s plans going forward.
Q: What is the significance of Intel Xeon Phi coprocessor support to Rogue Wave’s products and customers?
The Intel Xeon Phi represents an important point in the development of processors, both for users who have traditionally been part of the High Performance Computing (HPC) community, as well as users in the commercial community who demand performance. Industry analysts have predicted for a while that multi-core will give way to many-core processors. With the Intel Xeon Phi coprocessor, built on Intel® MIC (Many Integrated Cores) architecture, Intel provides a way for developers to explore and start to leverage the power of massive numbers of slower processing cores. Those who are able to find and exploit more opportunities for parallelism in their code will be able to take advantage of a many-core processor. For some users this will mean leveraging high performance components, such as class libraries, and for others it will mean refining algorithms to run in parallel. As the community undertakes this project, Rogue Wave’s tools and libraries will enable developers to more quickly and confidently port and tune their applications for the Intel MIC architecture.
Before developers can fully take advantage of a new architecture, they first need to get their code running on it. The amount of effort this requires can vary and could require modifying interactions with the application’s environment, third party libraries, data sources, and many other resources. Next, because the Intel Xeon Phi coprocessor has a many-core architecture, developers also need to parallelize, tune, and scale their code. This is likely a task that many developers have yet to tackle. As every developer knows, whenever code is changed, the opportunity for bugs to be introduced occurs. Running on a many-core system is a great step, but running efficiently and with high performance is the real goal. Tools to help developers do that tuning are essential.
Q: Which products has Rogue Wave committed to support the Intel Xeon Phi coprocessor?
Now, more than ever, developers of applications for the Intel Xeon Phi coprocessor will need tools and components, like Rogue Wave’s, to improve their productivity and increase the performance of computational applications by helping them take advantage of parallelism in applications. We have announced support in two class library products and two software development tools. The libraries are SourcePro® C++ and IMSL® C Numerical Library. SourcePro has been used in enterprise software systems for more than 20 years, while IMSL has been providing advanced analytics for more than 40 years. The software development tools are TotalView® and ThreadSpotterTM. TotalView is the most widely used parallel debugger – very common in HPC communities and expanding rapidly into commercial verticals. ThreadSpotter is a processor cache optimization tool that helps developers find and correct inefficiencies in their code. These products are designed to help developers write fast, parallel code, making them part of a critical toolset for users who are looking to integrate the Intel Xeon Phi coprocessor into their systems.
Q: More specifically, how will Rogue Wave’s TotalView debugger help developers utilizing the Intel Xeon Phi coprocessor in their applications?
In addition to providing a critical view into their codes, TotalView gives developers essential control over their applications running on the Intel Xeon Phi coprocessor. For some applications that run natively on the Intel Xeon Phi coprocessor, this means being able to view and control all the OpenMP threads, MPI processes, or a combination of threads and processes that make up the program. TotalView works at the MPI level and will work out of the box with applications that leverage two or more Intel Xeon Phi coprocessors on a single server, or many Intel Xeon Phi coprocessors in a cluster configuration.
Some users will want to start with a program that runs on a ‘regular’ x86 host and take advantage of the Intel offload directives (LEO) to dispatch highly parallel computations to the Intel Xeon Phi coprocessor. These applications are effectively heterogeneous, leveraging both the smaller number of higher clock speed host processors and the larger number of lower clock speed Intel Xeon Phi processors, for the kinds of computations they are best suited. TotalView will give a full view of what is happening on both sides of the computation, allowing developers to make sure that data is transferred correctly and that the different parts of the computation are being orchestrated correctly.
Q: What is the availability of the Intel Xeon Phi coprocessor support in each of these products?
TotalView is the furthest along, with early access support available in the next release schedule for this quarter. Full certification and support for SourcePro and the IMSL C Numerical Library will be completed in a future release. We can work with customers on an individual basis for early use and I encourage them to contact us for details. For ThreadSpotter, we need to complete our mathematical model of the Intel Xeon Phi coprocessor cache behavior before announcing the product release schedule.
Q: What made Rogue Wave decide to add such broad support for a yet-to-be-released chip architecture?
That’s a great question. It’s no secret that everyone always wants better performance for their software. When NVIDIA® came out with their accelerator cards and CUDA™, interest was dramatic. Some people adopted it early, and we continually see more customers adding CUDA to projects. For some, the performance boost has been dramatic with good ROI. Many didn’t take the leap, but that doesn’t mean they don’t want and need better performance. When Intel announced the MIC architecture, interest was overwhelming. If customer enthusiasm is an indicator, then the Intel Xeon Phi coprocessor will be widely adopted across many industries. Since Rogue Wave anticipated this demand, we started our work early on, because helping our customers be more productive and achieve better performance is a cornerstone of our mission.
Q: What has Rogue Wave’s experience been working with the Intel Xeon Phi coprocessor?
Fantastic. I know that’s not giving much detail, but it’s really been a great experience. We were able to get TotalView up and running, debugging a process executing on the Intel Xeon Phi coprocessor, within a week. I don’t want to give any illusions that we were done in a week, as there’s obviously a lot that goes into a complete port for new hardware. However, the fact that we had a prototype fundamentally working within a matter of days was very exciting and shows how “port friendly” the environment is. For our SourcePro and IMSL products, they were architected to be highly portable from the beginning, and run across many chip architectures and operating systems today. Because of this inherently portable design, we’ve had great initial results with the Intel Xeon Phi coprocessor.
Q: What type of organizations would benefit the most from using Rogue Wave components such as the IMSL Numerical Libraries in applications running on the Intel Xeon Phi coprocessor?
The biggest advantage to using the IMSL Numerical Libraries will be gained from organizations that are looking to increase the performance of computational applications by taking advantage of parallelism that can be achieved by utilizing the Intel Xeon Phi coprocessor. The more the code is vectorized, the better the performance increase will be. Actually, using IMSL and vectorizing code will also give benefits on other architectures as well, due to technologies, such as AVX acceleration on x86 processors, so there’s no downside to doing that work.
Q: What about Rogue Wave’s debugging and memory optimization tools?
Organizations creating highly parallel code will benefit the most from the TotalView debugger and ThreadSpotter. One of TotalView’s biggest strengths is its ability to present parallel execution in an intuitive and useful way. When you have tens, hundreds, or thousands of processes/threads running simultaneously, keeping track of what’s going on is very challenging without a tool like TotalView. ThreadSpotter is great at directing developers to areas where their code thrashes the cache, wastes cache lines, or has cross-core cache pollution. The more threads/processes an application has running, the more opportunities these inefficiencies have to wreak havoc.
Q: What can we expect from Rogue Wave next?
We are consistently innovating at both the product feature level, as well as expanding our platform support. As cutting-edge, interesting architectures emerge, we consider them for adoption based on customer demand and applicability to our products. We are also a very acquisitive company, and continue to evaluate products and companies that help customers create parallel, data-intensive applications. We have a long-standing reputation of delivering quality products that make developers more productive and we are committed to upholding this effort.
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Read more...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
Read more...
Supercomputing veteran, Bo Ewald, has been neck-deep in bleeding edge system development since his twelve-year stint at Cray Research back in the mid-1980s, which was followed by his tenure at large organizations like SGI and startups, including Scale Eight Corporation and Linux Networx. He has put his weight behind quantum company....
Read more...
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
Read more...
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
Read more...
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
Read more...
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
Read more...
May 08, 2013 |
For engineers looking to leverage high-performance computing, the accessibility of a cloud-based approach is a powerful draw, but there are costs that may not be readily apparent.
Read more...
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.