October 23, 2012
The acceleration of Ethernet performance over the past few years and its subsequent entry into world of datacenter fabrics is changing the landscape of high performance interconnects. At the recent Linley Tech Processor Conference, networking sage Andy Bechtolsheim talked about the how he sees the technology playing out over the next decade.
An EE Times article, penned by Rick Merritt, covered Bechtolsheim's conference presentation in nice detail and is worth a read. Bechtolsheim's main themes encompassed everything from network buffer sizes to the changing economics of the switch-making business.
The divergence between the breakneck pace of transistor shrinkage (Moore's Law) and the more leisurely performance increase in I/O bandwidth. According the Bechtolsheim, while chips are doubling their transistor density ever couple of years, network bandwidth is only doubling every four years.
To take up the slack, he said, network protocols and applications have to be optimized. In lieu of that, network switch design has to be improved, which to Bechtolsheim is all about right-sizing buffers.
The networking guru decries the proliferation of optical interconnect standards in the pipeline that are ostensibly being developed to deal with the upcoming 100GbE networks. Bechtolsheim thinks the five standards in motion today are just too many.
Nevertheless, he's bullish on Ethernet technology, and the switch biz, in general -- not too surprising considering the amount of time and money he has devoted to Arista, his Ethernet switch startup. Bechtolsheim notes that the current boom in datacenter buildout is fueling a lot of networking growth, which is projected to triple the switch market from $4-5 billion in 2010 to $15 billion by 2015.
He also notes that economics is forcing everyone to use merchant chips, as Arista does now, and even network behemoths like Cisco won't be able to afford custom ASICs for their own switches. That will likely shrink the number of such vendors to just a handful over the next few years. Regardless, he says, chip design will be the critical technology for the networking business going forward.
Full story at EE Times
Large-scale, worldwide scientific initiatives rely on some cloud-based system to both coordinate efforts and manage computational efforts at peak times that cannot be contained within the combined in-house HPC resources. Last week at Google I/O, Brookhaven National Lab’s Sergey Panitkin discussed the role of the Google Compute Engine in providing computational support to ATLAS, a detector of high-energy particles at the Large Hadron Collider (LHC).
Read more...
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Read more...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
Read more...
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.