Visit additional Tabor Communication Publications
November 09, 2012
AUSTIN, Texas - Intel will announce the details of the first release of its Many Integrated Core (MIC) coprocessors, the Intel Xeon Phi, at the international Supercomputing 2012 (SC12) conference in mid-November, at which point many in industry and academia will begin using this innovative technology. The Texas Advanced Computing Center (TACC) at The University of Texas at Austin was selected as the first installation to deploy the new MIC technology at large scale in the forthcoming Stampede supercomputer, funded by the National Science Foundation, and is launching extensive training and technical information activities to help users take advantage of this imminent, innovative technology.
"Intel Xeon Phi is going to be an exceedingly popular and powerful mainstream technology, and we are excited to help the world figure out how to use it most effectively — as soon as possible," said Jay Boisseau, TACC Director.
Stampede is scheduled to go into full operation on January 7, 2013, with 6400 Dell C8220X nodes comprising 12,800 Intel Xeon E5 ("Sandy Bridge") processors plus several thousand 'special edition' Intel Xeon Phi (MIC) coprocessors. The Xeon Phi coprocessors alone will provide over 7 petaflops of performance, making Stampede a tremendously powerful computational resource for the open science community.
The Intel Xeon Phi coprocessor employs a new design that promises greater performance while using less energy per operation. The coprocessors have many (more than 50) small cores and massive parallel threading capabilities, allowing many more computations to be performed simultaneously than on a traditional CPU. However, unlike other many-core accelerators such as GPUs, the Xeon Phi is based on the x86 architecture — the dominant architecture in enterprise, consumer, and research computing. The Xeon Phi is designed to be coded using common programming languages like C/C++ and Fortran, and common parallel programming tools like OpenMP and MPI. This out-of-the-box functionality was one of the characteristics that attracted TACC to the new technology and that convinced them to include the Xeon Phi as the "innovative capability" in their successful proposal to the National Science Foundation for the Stampede system.
The hands-on testing of MIC technology on behalf of the computational community began in early 2011, when TACC and other institutions started working with a prototype software development platform. TACC has been testing pre-release versions of the Intel Xeon Phi coprocessor and associated software stacks over the last few months in support of their ongoing Stampede deployment. Leading experts like Karl W. Schulz, TACC Director of Scientific Applications, were able to get large codes to compile, run, and scale on the MIC technology in hours.
"We are at an exciting evolutionary crossroads at TACC in the continued pursuit of increased performance per watt necessary to ultimately achieve exascale computing," Schulz said. "Stampede provides not only a boost in the scale and performance of traditional x86/InfiniBand compute infrastructure, but it also provides the academic community with a convenient mechanism to incrementally leverage coprocessors to exploit data and algorithmic parallelism using familiar coding constructs."
TACC's expertise lies in optimizing the performance and tuning of its HPC systems and software stack so that scientists can achieve maximum research productivity. The center employs 37 PhDs, more than a third of them focused on HPC performance. Together, they are developing a set of tools and techniques to boost the experience of users on the heterogeneous system, and will begin supporting users worldwide with new training workshops, documentation, and hands-on code optimization.
"MIC's support of standard programming languages and tools allow almost any code to be compiled for MIC and natively executed on MIC," explained TACC research staff member Lars Koesterke. "In fact, since the Xeon Phi development environment supports native C/C++ and Fortran cross-compilation and direct login access to the coprocessor, the porting process is generally very straightforward." Koesterke notes, however, that optimization efforts should still be considered after initial porting to maximize vectorization and parallel efficiencies on this new architecture. These are focus areas of early TACC training and documentation.
"While the process of porting code to MIC can begin with a simple recompile," Koesterke continued, "this is usually so easy that some users may be fooled into expecting that this is all the effort needed, if they are not informed of the optimization techniques for using MIC effectively in advance. Such users may perceive MICs either as tedious to program for, or as useless, but this false perception is a result of how easy the initial porting effort is — which is in reality a good thing, since optimization effort can begin that much sooner. But users must still optimize to achieve the full performance potential of the MICs, as with any new processor technology."
Community experiences and training on the principles and programming paradigms relevant to the MIC architecture began at the two-day "TACC-Intel Highly Parallel Computing Symposium" in April and continued this week with training sessions at Cornell University, a partner on the Stampede project, on November 6. On Monday, November 11 at the Peery Hotel in Salt Lake City, TACC staff will lead a special tutorial on how to use the Xeon Phi coprocessors on Stampede. The "Sneak Preview" during SC12 will include an overview of the Stampede architecture and Intel Xeon Phi coprocessor, discussions about programming models and performance tuning on Stampede, and hands-on exercises on the system. Additionally, TACC director Jay Boisseau, as well as the other primary investigators on Stampede, will give short presentations in the TACC booth on both Tuesday and Wednesday of SC12. [For a full list of Stampede-related talks at SC12, visit the "TACC@SC12" website.]
In December and January, leading up to the launch of Stampede on January 7, both TACC and Cornell will offer training, first to early users and then to anyone interested in learning about the new technology. Information from the training will be made available online, helping to prepare the research community for Stampede.
In the spring, TACC staff will teach a new class to graduates and undergraduates at The University of Texas at Austin on hybrid programming for heterogeneous systems like Stampede. Taught in the Division of Statistics and Scientific Computing, the class will introduce students to the programming models most relevant to systems that use more than one type of processor architecture, which are becoming the mainstay of the largest HPC systems internationally.
To assist in the transition to a new system, TACC develops comprehensive user guides for each of its resources, anticipating questions, explaining new capabilities or aspects of the system, and guiding users through the process of accessing and running jobs on the system. In early December, TACC will release the Stampede user guide, including documentation on the full configuration of the system. Shortly after, a friendly user period will commence and some of the most experienced users from the HPC community will be invited to test, evaluate and provide feedback on the operation of the system.
"My group can't wait to get its hands on Stampede," said Omar Ghattas, director of the Center for Computational Geosciences in the Institute for Computational Engineering and Sciences at The University of Texas at Austin and a leader in the computational science community. "This system will be a great boon for our work on solving inverse problems for large-scale models, where observational data are used to infer uncertain parameters in the models, and hence characterize uncertainties in their predictions."
The rise of multi-petaflop and eventually exascale systems comes with intense power needs, and a need to take advantage of parallelism on every level. Systems like Stampede that use very fast, power efficient many-core coprocessors like the Intel Xeon Phi represent an evolutionary point on the way forward.
"Stampede's order of magnitude leap in performance relative to what had been available to NSF researchers comes at the right time," Ghattas said. "This system's impact will be felt across a spectrum of fields including astronomy, astrophysics, biology, climate, energy, earth sciences, infrastructure, manufacturing, materials, medicine, and social sciences, to name a few."
Source: The Texas Advanced Computing Center
Contributing commentator, Andrew Jones, offers a break in the news cycle with an assessment of what the national "size matters" contest means for the U.S. and other nations...
Today at the International Supercomputing Conference in Leipzing, Germany, Jack Dongarra presented on a proposed benchmark that could carry a bit more weight than its older Linpack companion. The high performance conjugate gradient (HPCG) concept takes into account new architectures for new applications, while shedding the floating point....
Not content to let the Tianhe-2 announcement ride alone, Intel rolled out a series of announcements around its Knights Corner and Xeon Phi products--all of which are aimed at adding some options and variety for a wider base of potential users across the HPC spectrum. Today at the International Supercomputing Conference, the company's Raj....
Jun 19, 2013 |
Supercomputer architectures have evolved considerably over the last 20 years, particularly in the number of processors that are linked together. One aspect of HPC architecture that hasn't changed is the MPI programming model.
Jun 18, 2013 |
The world's largest supercomputers, like Tianhe-2, are great at traditional, compute-intensive HPC workloads, such as simulating atomic decay or modeling tornados. But data-intensive applications--such as mining big data sets for connections--is a different sort of workload, and runs best on a different sort of computer.
Jun 18, 2013 |
Researchers are finding innovative uses for Gordon, the 285 teraflop supercomputer housed at the San Diego Supercomputer Center (SDSC) that has a unique Flash-based storage system. Since going online, researchers have put the incredibly fast I/O to use on a wide variety of workloads, ranging from chemistry to political science.
Jun 17, 2013 |
The advent of low-power mobile processors and cloud delivery models is changing the economics of computing. But just as an economy car is good at different things than a full size truck, an HPC workload still has certain computing demands that neither the fastest smartphone nor the most elastic cloud cluster can fulfill.
Jun 14, 2013 |
For all the progress we've made in IT over the last 50 years, there's one area of life that has steadfastly eluded the grasp of computers: understanding human language. Now, researchers at the Texas Advanced Computing Center (TACC) are utilizing a Hadoop cluster on its Longhorn supercomputer to move the state of the art of language processing a little bit further.
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?
Join our webinar to learn how IT managers can migrate to a more resilient, flexible and scalable solution that grows with the data center. Mellanox VMS is future-proof, efficient and brings significant CAPEX and OPEX savings. The VMS is available today.