January 29, 2013
MOUNTAIN VIEW, Calif., Jan. 29 – Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of its multiprotocol DesignWare Enterprise 10G PHY IP to address the connectivity needs of a broad range of high-end, energy efficient networking and computing applications. Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express (PCIe) 3.0 and 10GBASE-KR, for a flexible interconnect solution. The new DesignWare IP also implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet, giving designers a proven, scalable solution to address the growing demand for additional networking bandwidth in high-speed systems-on-chips (SoCs).
“As the fastest growing protocol in the enterprise and data center market, 10 Gigabit Ethernet is becoming a key backplane interface,” said Jag Bolaria, senior analyst at The Linley Group. “Our research indicates over 25% CAGR through 2016 in the number of 10 Gigabit Ethernet ports deployed in the enterprise and data centers. The growth of 10GBASE-KR ports, combined with the rapid adoption of integrated PCI Express 3.0 in multiprocessor cores, elevates the importance of Synopsys’ multiprotocol SerDes IP for designers developing ASICs that embed high-speed interfaces.”
The DesignWare Enterprise 10G PHY offers a modular design with a highly configurable physical coding sub-layer (PCS) capable of bifurcation and aggregation. Its analog front-end includes multi-tap decision feedback equalization (DFE) and continuous time linear equalization (CTLE), which enhance signal integrity in high throughput communication channels. The DesignWare Enterprise 10G PHY is optimized for area, power and width to ease integration into the rest of the SoC.
The Enterprise 10G PHY is part of Synopsys’ complete PCI Express 3.0 and 10G Ethernet solutions, each of which include a PCS, controller and verification IP. The PHY’s support for 10GBASE-KR includes physical medium attachment (PMA), auto negotiation (AN), PCS, forward error correction (FEC) and energy-efficient Ethernet (EEE). Providing comprehensive 10GBASE-KR support, including the optional EEE and FEC features, enables SoC designers to single-source IP solutions to help ensure interoperability while reducing risk and time-to-market.
“From the start, we designed the DesignWare Enterprise 10G PHY to enable a flexible range of implementations with scalable data rates, support all major networking and computing protocols, and be available at multiple leading foundries,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “Synopsys’ complete PCI Express 3.0 and 10G Ethernet IP solutions enable design teams to integrate ultra-high data throughput functionality into their devices with less risk and without compromising time-to-market.”
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries and configurable processor cores. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys’ HAPS FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys’ Virtualizer virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to following traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk.
About Synopsys
Synopsys, Inc. accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems.
-----
Source: Synopsys
Large-scale, worldwide scientific initiatives rely on some cloud-based system to both coordinate efforts and manage computational efforts at peak times that cannot be contained within the combined in-house HPC resources. Last week at Google I/O, Brookhaven National Lab’s Sergey Panitkin discussed the role of the Google Compute Engine in providing computational support to ATLAS, a detector of high-energy particles at the Large Hadron Collider (LHC).
Read more...
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Read more...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
Read more...
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
Read more...
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
Read more...
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
Read more...
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
Read more...
May 08, 2013 |
For engineers looking to leverage high-performance computing, the accessibility of a cloud-based approach is a powerful draw, but there are costs that may not be readily apparent.
Read more...
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.