HPCwire: Looking Back Over the Last Year in HPC

The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing

HPCwire >> Off the Wire

June 30, 2006

Looking Back Over the Last Year in HPC

by Thomas Sterling

Page: 1 of 4
1 | 2 | 3 | 4 All »

Introduction

Every year, the International Supercomputing Conference (ISC) reviews the major directions and key advances in the field of high performance computing during the preceding year -- from the previous June to the time of the current conference. At ISC 2006, significant accomplishments since June of 2005 were discussed, touching on some of the most interesting events and trends. Unlike last year, the year just concluded has seen no new major breakthroughs in high performance computing.

But such an observation would obscure the important and rapid progress that was achieved along the new path first established during the previous year. Described then as "high density computing" this important change in direction has emerged as the dominant strategy for continuing to exploit Moore's Law. Taking two widely variant forms, high density computing achieves increased performance with continued device density increases while limiting the growth in power consumption that has characterized recent microprocessor product deployment. Multi-core components, integrating multiple processor cores on a single chip, are driving this new path. A second strategy is heterogeneous computing mixing processors of diverse form and function to provide different modalities of superior sustained performance. These two techniques are being employed, sometimes in combination, as the basis for perhaps the most notable direction of the last year: the beginning of the campaign to develop general-purpose Petaflops scale computer systems by the end of this decade.

While serious consideration about the means and methods for reaching a Petaflops capability has been explored since at least 1994, this year marked a turning point with the preparation for projects to develop such machines. But the year also saw, perhaps less dramatically but still of importance, continued improvement and maturation of many of the foundation elements of the HPC arena including new releases of several heavily relied upon software packages including more than one release of MPI, a mainstay of parallel programming. These and other aspects of this year's progress are highlighted in this brief discussion.

Multi-Core

Historically, since the 1980s, microprocessor technology has moved toward very powerful single chip uni-processor designs. First limited by available logic devices and later by latencies due to on-chip execution pipelines and off-chip memory accesses, microprocessor architecture has grown to highly complex systems. Unfortunately, the point of diminishing returns has been reached such that the addition of more devices results in ever decreasing performance improvement. At the same time, power consumption continued to increase with increases in clock speed and total device count to a point that was judged bordering on impractical for future commercial systems.

Enter multi-core. Last year, commercial vendors introduced dual-core components. Performance gain would no longer be achieved through ever larger and more complicated processor design but rather through the integration of multiple processors on the same component chip. Over the last year, multi-core has come to dominate both mainstream commercial systems -- reaching as far down as the laptop -- and supercomputer system design. The emerging generation of MPPs and clusters are all employing multi-core processor components to deliver sustained growth in performance. These include the IBM Blue Gene/L which now dominates the highest high end of the Top500 list, the next generation of Cray XT3 systems, and commodity clusters from more than one vendor using Intel and AMD 64 bit extended x86 architectures. While, the majority of such systems are dual-core, next generation systems are rapidly moving to quad-core. And it is expected that this trend will continue with Moore's law over several iterations.

However, it is recognized that the shift to multi-core brings with it its own challenges, especially for the mainstream markets. In a sense, the HPC community is better prepared for multi-core than the general commercial markets because the shift to parallel processing demanded by the new technology trend is a mainstay for supercomputing. Even for the world of supercomputing, this trend to multi-core will impose a demand for increasing parallelism. If, as is expected, this trend continues, then the amount of parallelism required of user applications may easily increase by two orders of magnitude over the next decade. Also, with more processors being put on the same die, the ratio of off-chip communications demand to I/O pins bandwidth is getting worse, making the exploitation of locality even more critical than before. But with more cores on a chip, the allocation of caches is made more complicated with smaller L1 caches per core and possibly fragmented shared L2 or L3 caches. With little or no architecture support for managing global parallelism, these challenges will have to be addressed by new software methods or more extreme application programmer resource management.

Heterogeneous Computing

This year has seen a marked increase in interest in heterogeneous computing for high performance. Spawned in part by the significant performances demonstrated by special-purpose devices such as graphical processing units (GPU), the idea of finding ways to leverage these industry investments for more general-purpose technical computing has become enticing with a number of projects, mostly in academia but also some work in national laboratories in many countries dedicating time to this. But the move towards heterogeneous computing is driven by more than the perceived opportunity of "low hanging fruit."

Page: 1 of 4
1 | 2 | 3 | 4 All »

Article Tools

Share Options

(Digg, Technorati, more)

Subscribe

Subscribe to HPCwire

Discussion

There are 0 discussion items posted.

Join the Discussion

You must be a registered user in order to comment on HPCwire stories.

Members enjoy:

	Access to Special Content, including Podcasts, Webcasts, and Whitepapers and more!
	Ability to take an active role in the discussions that are shaping the HPC technology discipline!
	Special offers available only to HPCwire members!

Become a Registered User Today!

Registered Users Log in Here to Comment

Email Address:	Password (case sensitive)

Remember me	Forgot Password?

RSS Feeds

Feeds by Topic

Feeds by Industry

Feeds by Content Type

Feature Articles

The Week in Review

C-DAC announces plans for a petaflop system; IBM researchers are working on vertical integration techniques to extend Moore's Law another 15 years. We recap those stories and more in our weekly wrapup.
Read More...

Moscow State University Supercomputer Has Petaflop Aspirations

The Moscow State University supercomputer, Lomonosov, has been selected for a high-performance makeover, with the goal of tripling its processing power to achieve petaflop-level performance in 2010. T-Platforms, who developed and manufactured the supercomputer, is the odds-on favorite to lead the project.
Read More...

Intel Ups Performance Ante with Westmere Server Chips

Right on schedule, Intel has launched its Xeon 5600 processors, codenamed "Westmere EP." The 5600 represents the 32nm sequel to the Xeon 5500 (Nehalem EP) for dual-socket servers. Intel is touting better performance and energy efficiency, along with new security features, as the big selling points of the new Xeons.
Read More...

Read more HPCwire features...

Top Headlines

Australia Commissions Cray Supercomputer

Mar 19 | OfficialWire | New super to support intelligence work Down Under. Read more...

Intel Partners See 'Easy' Upgrade Path With Xeon 5600 Chips

Mar 18 | ChannelWeb | Westmere parts already showing up in HPC machines. Read more...

AMD: OEMs primed for Opteron 6100s

Mar 17 | The Register | But what about the tier ones? Read more...

Arrival of the Desktop Supercomputer

Mar 17 | Cadalyst Magazine | A new generation of workstations is changing the nature of technical computing. Read more...

Scheduling HPC In The Cloud

Mar 17 | Linux Magazine | Latest iteration of Sun Grid Engine able to tap into Cloud. Read more...

Read more headlines...

Featured Whitepapers

Virtualization for Aggregation And The vSMP Architecture™

Jan 12 | | In-depth look at vSMP Foundation server virtualization technology, technical implementation, use cases and capabilities. The technical whitepaper provides an architectural overview and details on the three vSMP Foundation products: vSMP Foundation for SMP, vSMP Foundation for Cluster and vSMP Foundation for Cloud.

Copper Cable Technologies for High Performance Computing

Jan 18 | | This white paper discusses Gore’s copper cable assemblies, and how they continue to exceed the standards for providing reliable, cost-effective solutions for high-performance computer applications.

View the White Paper Library

Multimedia

Webcast: Virtualized Data Center Roundtable

Join this online panel discussion for live Q&A with leading industry experts, analysts, and end-users to discuss the latest innovations, best practices, barriers to implementation, and measurable benefits of server virtualization with a particular focus on today's real world solutions.

Webcast: Watch SC09 Birds of a Feather Video: Scalable Fault-Tolerant HPC Supercomputers

Learn about scalable fault-tolerant architectures and examples of energy efficient and scalable supercomputing clusters using dual QDR InfiniBand to combine capacity computing with network failover capabilities with the help of programming languages such as MPI and a robust Linux cluster management package.

Webcast: High Performance Computing for a Smarter Planet

LIVE@SCO9: The IBM team discusses new innovations in hardware, software and services that help clients better understand their workloads and get insight from their R&D efforts. Technology demonstrations include the soon-to-be-released Power7 HPC processor, the DCS990 system with 2.4 petabytes of storage, the xCAT management tool, secure HPC cloud computing and more. Winners of two HPCwire Readers' and Editors’ Choice Awards! Take the IBM virtual tour at SC09 or more information go online to: http://www-03.ibm.com/systems/deepcomputing/sc09.html