HPCwire: Alchip Unveils First Silicon of 512-Core Chip

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December 15, 2006

Alchip Unveils First Silicon of 512-Core Chip

In collaboration with the University of Tokyo and Taiwan Semiconductor Manufacturing Company (TSMC), Alchip Technologies, a fabless ASIC company, has announced its first silicon success of the SING processor for GRAPE-DR, a next-generation supercomputer design that is targeting a performance goal of two petaflops. The SING chip features 512 CPUs with over 60 million logic gates and 10 million bits of SRAM utilizing TSMC's 90nm process and flip-chip package technology.

The GRAPE series are among the world's fastest supercomputers and have been awarded the Gordon Bell Prize six times. The GRAPE systems have yielded simulation results used worldwide for scientific research in exploring the planet and galaxy.

GRAPE-DR is a research project funded by the University of Tokyo, National Astronomical Observatory of Japan, Institute of Physical and Chemical Research, NTT Communications plus corporations and research organizations. Its goals are to construct a two petaflops computing engine and global research infrastructure utilizing multi-10 Gbps networks by 2008. The GRAPE-DR machine is designed to compute more than 31 times faster than its predecessor, GRAPE-6 (64 trillion computations per second), and to support general-purpose computing.

According to Alchip, development of the SING processor was very challenging due to its large gate count complexity and performance target. The SING processor contains over 60 million logic gates and is designed to run at 500 MHz while consuming 50 to 60 watts of power. Alchip was responsible for the complete design integration which includes physical, electrical, timing and thermal design of the System-on-Chip (SoC) project. The chip adopted TSMC's 90nm eight-layer metal process with a silicon redistribution layer (RDL) in a flip-chip BGA package. Alchip's divide-and-conquer methodology was used to partition the design into three levels of hierarchy for parallel implementation. Alchip's on-chip clocking distribution structure achieved minimum global clock skew on the scale of 18mm by 18mm die size. It enabled high speed operation by avoiding serious nanometer on-chip variation (OCV) which can affect circuits performance. Close collaboration with the customer allowed Alchip to provide effective design and packaging solutions to achieve a one-pass design tapeout and a one-pass silicon success.

"Having selected Alchip as our SoC development partner, we are extremely delighted and satisfied with Alchip's on-time and one-pass silicon success delivery of SING chip," said Professor Kei Hiraki of the University of Tokyo. "Alchip demonstrated superior design and manufacturing capabilities and supported the development of GRAPE-DR project well. With Alchip's efforts, we are able to test, demonstrate and bring GRAPE-DR to the market on time."

"TSMC supports a broad range of existing and emerging applications," said Makoto Onodera, president of TSMC Japan. "The GRAPE-DR project achieved the first silicon success and marks a major collaborative milestone among private, public, and academic segments."

"Alchip is pleased to provide total SoC solutions to the University of Tokyo for the fastest supercomputer in the world," said Kinying Kwan, chairman, president and chief executive officer of Alchip. "The first silicon success of this complex and challenging chip illustrates Alchip's superior SoC design capabilities in cutting-edge technologies and demonstrates our robust turnkey infrastructure that seamlessly integrates physical design, IP, fabrication, packaging and testing solutions. We will continue to delight our customers by powering them with the fastest time-to-market and the lowest total cost of ownership."

For information about the GRAPE-DR project, visit http://grape-dr.adm.s.u-tokyo.ac.jp/index-en.html or contact Professor Kei Hiraki at hiraki@is.s.u-tokyo.ac.jp.

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