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February 09, 2007
P.A. Semi Samples Power-Efficient High-Performance Chip
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SANTA CLARA, Calif., February 5, 2007 -- P.A. Semi, Inc., a fabless semiconductor startup developing the high-performance, low-power PWRficient processor family-today announced that, after nearly three years of development, it is now sampling its dual-core PA6T-1682M PWRficient processor based on the Power Architecture technology. The PWRficient processor is engineered to deliver unprecedented performance per watt, consuming just 5-13W of power (typical) at 2 GHz, making it 300-400 percent more power efficient than competing processors. P.A. Semi also announced more than 100 initial customer engagements, with 10 alpha customers and associated development and support infrastructure.
"The industry recently awoke to the need to move to energy-efficient processors, and the release of our first PWRficient processor, which is up to 400 percent more power-efficient than other high-performance processors, marks a significant milestone for P.A. Semi to satisfy those needs," says Dan Dobberpuhl, president and C.E.O. of P.A. Semi. "Successfully delivering on the PWRficient processor's aggressive power and performance metrics, while also building out our support and sales infrastructure, has helped to generate strong customer interest and widespread adoption."
CUSTOMER TRACTION AND TARGET MARKETS
The PWRficient processors' performance, cost and energy efficiency have seen major customer traction in the multibillion-dollar embedded computing and control markets since its formal announcement in fall of 2005. P.A. Semi has secured more than 100 customer engagements and 10 alpha customers, including Curtiss-Wright Controls Embedded Computing, Extreme Engineering Solutions (X-ES), Mercury Computer Systems, Performance Technologies, Splitted-Desktop Systems and Themis Computer. Additionally, P.A. Semi is working with all the top businesses in a broad range of market segments, including networking, wireless infrastructure, storage, and the military and aerospace markets.
This deployment is underpinned by a worldwide sales force that includes both direct and indirect sales, with Nu Horizons Electronics Corporation taking the lead on all distribution activities in the U.S., UK, India, Australia and China, and Clavis Company, a division of Macnica, Inc., heading up distribution in Japan. Additionally, more than 100 sales persons, via P.A. Semi's representatives, are covering all areas of the globe. A complete list of representatives by geographic region is available at www.pasemi.com.
"In recent years, the sophistication and types of services applied to packets and streams in the Internet, and especially intranets, have redoubled at the same time that overall traffic is growing rapidly," said John Wakerly, consulting professor at Stanford University and former CTO of Cisco Systems Routing Technology Group. "The result is an astonishing increase in the number of general-purpose-CPU instructions that must be executed within the network, creating a crucial need for high-performance, I/O-rich multicore microprocessors that can pack large amounts of computing and packet-handling power within a small power envelope, such as those offered by P.A. Semi. The need for such 'platform processors' extends well beyond traditional routing control planes and data planes to the growing array of embedded network services, such as security, authentication, content customization, voice over IP, unified messaging and converged video solutions."
PWRFICIENT PA6T-1682M
The P.A. Semi PA6T-1682M, developed in 65-nanometer process technology, is a 64-bit dual-core microprocessor, designed from the ground up, based on the company's Power Architecture license from IBM. The 1682M integrates what is typically a three- to five-chip-set platform into a single chip, called a "platform processor." Total device power dissipation is 5-13W (typical), and worst-case power is 25W, with both CPUs running at 2 GHz and all peripherals active. This is three times to four times lower power than other processor solutions implemented in 65-nanometer process technology with equivalent peripherals support.
The 1682M features two 2-GHz processors (each with its own dual-integer, floating-point, and VMX vector-processing units), 2 MB of level two cache, two DDR-2 memory controllers and hardware assist engines for TCP/IP acceleration, security, CRC checksum and XOR computation. The device also integrates a flexible I/O subsystem that supports eight PCI Express controllers, two 10-Gigabit Ethernet controllers and four Gigabit Ethernet controllers that share 24 configurable SERDES lanes.
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