The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing
April 04, 2008
XtremeData, Altera Demo In-Socket FPGA Accelerator at IDF
1 | 2 All »
XD2000i accelerator first based on multiple Stratix III FPGAs
SCHAUMBURG, Ill., April 2 -- At the Intel Developer Forum (IDF) now in progress in Shanghai, XtremeData, Altera, and Intel Corporation are demonstrating acceleration of a full double-precision floating point simulation of a Monte Carlo financial simulation analysis. This demonstration for the first time combines the Intel QuickAssist Technology, Altera's high performance Stratix III FPGA family, XtremeData's XD2000 family of In-Socket Accelerators (ISA), and the new XtremeRNG library of building blocks for random number generation (RNG) to significantly accelerate financial and scientific Monte Carlo applications.
"Altera is working closely with XtremeData to harness the double-precision floating point capabilities of our high performance FPGAs," said Dr. Misha Burich, senior vice president of research and development at Altera. "Stratix III FPGAs offer an almost unlimited flexibility in dataflow architectures and is an ideal solution for our customers in the financial, military and medical markets to implement arithmetic functions or to accelerate a system by off-loading a datapath that cannot be optimally implemented in a stand alone processor."
Monte Carlo simulation of financial instruments consists of three steps: Pathway Generation, Pathway Evaluation, and Expectation/Computation. By combining the power of QuickAssist Technology and the XD2000i In-Socket Accelerator, XtremeData demonstrates that source code written within the QuickAssist abstraction framework can be re-targeted between the CPU and the FPGA without modifying the original source code.
Only the XD2000i family of in-socket accelerators successfully applies multiple FPGAs. XtremeData designed the module with three Altera FPGAs, one as a bridge to system resources, and the other two for running user applications. This industry-first design allows users to reconfigure the application FPGAs in-system, without rebooting the server. This lets system designers focus on getting algorithms working in the application FPGAs without needing to understand and trouble-shoot the system interfaces.
When XtremeData co-processor modules are integrated into commercial, off-the-shelf (COTS) servers, blade systems and ATCA boards, applications can be substantially accelerated via parallelization and pipelining. The XD2000i provides high-performance application acceleration ranging up to 10X versus alternative solutions, while simultaneously reducing overall system power consumption and latency. It is the ideal solution for accelerating applications such as algorithmic financial trading, market data, deep packet inspection, bioinformatics, military and video transcoding.
"The demonstration of Monte Carlo simulation on the XtremeData XD2000i In-Socket Accelerator using Intel QuickAssist Technology showcases a powerful FPGA co-processing solution," said Dylan Larson, director, server software and technology initiatives, Digital Enterprise Group, Intel Corporation. "The Intel QuickAssist Technology Accelerator Abstraction Layer allows customers to maintain a standard code base which can target accelerators, like the XD2000i, or Intel Xeon processor at run time."
Attendees visiting the XtremeData booth BU016 will see a live product demonstration of the XD2000i In-Socket Accelerator directly interfacing to the 64-bit Front-Side Bus (FSB), showcasing that key routines in the simulation can be executed on the Stratix III FPGAs residing on the ISA, the Xeon, or a combination of both, without changes to the overall application code.
Product Demonstration:
- XtremeData's ISA.
- Live data transactions across the FSB interface to the Stratix III FPGA XD Module.
- XtremeRNG -- Random Number Generator Library.
- Monte-Carlo -- European Options.
- Intel QuickAssist Technology.
- Retargeting between CPU and accelerator without changes to application code.
- Altera Stratix III FPGAs.
- Double-Precision Floating Point Features on the Enhanced Stratix III FPGA Family.
The Intel Xeon platform offers a high-bandwidth, low-latency interface to other processors and memory via the FSB interconnect. Placing the Stratix III FPGA in one of the Xeon sockets gives the coprocessor a high-speed link to memory as well as a fast connection to the host processor without requiring board modifications, thus providing a simple hardware integration path. Stratix III FPGAs provide the XD module with an abundant amount of logic and provides Intel-based systems with up to 2304 multipliers assessable via a fast FSB processor interconnect.
Article Tools
Share Options
(Digg, Technorati, more)
Subscribe
Sponsored Links
New Paper: Parallel Computing Without Parallel Programming
Learn how domain experts can run VHLL programs like MATLAB® on a variety of high-performance platforms without low-level reprogramming and how to work with the largest datasets and complex algorithms without sacrificing ease of use or reducing productivity.
RSS Feeds
Feeds by Topic
- Applications
- Developer Tools
- Interconnects
- Middleware
- Networks
- Processors
- Storage
- Systems
- Visualization
Feeds by Industry
Feeds by Content Type
Feature Articles
Spider Up and Spinning Connections to All Computing Platforms at ORNL
Spider, the world's biggest Lustre-based, centerwide file system, has been fully tested to support Oak Ridge National Laboratory's new petascale Cray XT4/XT5 Jaguar supercomputer and is now offering early access to scientists.
Read More...
Wolfram Alpha: A Web-Based Application That Embraced Supercomputers
Wolfram Alpha, the Web-based computational engine introduced in May, is not a traditional supercomputing application, but relies on supercomputers to satisfy its unique requirements.
Read More...
TeraGrid '09: Student Participation Soars
There was a new energy at this year's TeraGrid '09 conference thanks to an outstanding turnout for the student program. Thanks to support from the National Science Foundation, more than 100 high school, undergraduate and graduate students were able to participate in the conference.
Read More...
Top Headlines
3D Seismic Data: Taking a Smarter Approach to Interpretation
Jul 09 | Engineer Live | The demand for computational tools to underpin the 3D seismic interpretation process has never been more apparent. Read more...
Engineering Unemployment Soared in 2Q to 8.6%
Jul 08 | EE Times | Unemployment for U.S. engineers has reached record levels, according to government figures. Read more...
Gartner Adjusts 2009 IT Spend Downward Again
Jul 08 | Network World | Global spending for 2009 projected to drop 6 percent, for a total of $3.2 trillion. Read more...
Concurrent and Parallel Are Not The Same
Jul 08 | Linux Magazine | Portability or efficiency? Neither is guaranteed when writing explicit parallel code. Read more...
800 TFLOP Real-Time Ray Tracing GPU Unveiled, Not for Gamers
Jul 07 | Ars Technica | Japanese company builds custom ASIC to accelerate real-time ray traced rendering for the auto industry. Read more...
Featured Whitepapers
Parallel Computing Without Parallel Programming
Jul 10 | | Engineers, scientists, and other domain experts depend on the productivity enabled by very high-level language (VHLL) tools like MATLAB® and Python. However, as datasets grow larger and programs get more sophisticated, ordinary desktop computers can no longer keep up. The paper explores how to run VHLL programs on high-performance platforms without low-level reprogramming. Work with large datasets and complex algorithms without sacrificing ease of use or reducing productivity.
Building High Performance Computing in a Green and Modular Solution Building Block
Apr 14 | | Many HPC IT departments are feeling the rising pressure to deliver more capacity computing and performance while trying to reduce the total cost of ownership. This white paper discusses how an environmentally-friendly and open-standards HPC building block based computing system using flexible interconnect options helps address capacity computing needs.
Multimedia
Webcast: Dell Expands HPC Access and Adoption with Intel Cluster Ready Program
Source: Addison Snell, GM/VP, Tabor Research; sponsored by Dell
Many organizations that could benefit from the use of HPC clusters find that it is complicated to get the systems up and running because of limited IT resources or the complexities of the clusters themselves. Learn how the Intel Cluster Ready program, for which Dell was an original partner, seeks to address this challenge for entry level and mid-range HPC users.
Video White Paper: Architecting a Better Network Storage Solution
BlueArc's Titan architecture represents an evolutionary step in file servers by creating a hardware-based file system that can scale bandwidth, IOPS, and overall data capacity well beyond conventional software-based devices. With its ability to virtualize a massive storage pool of up to four usable petabytes of tiered storage, Titan can scale with growing data requirements, offering a competitive advantage for businesses, researchers, or other enterprises seeking to better manage data growth while still ensuring optimal performance.
Webcast: HPC Development Solutions: Sun Studio & Sun HPC ClusterTools
Sun Studio Compilers and Tools and Sun HPC ClusterTools allow you to create high performance parallel applications for OpenSolaris, Solaris and Linux. Sun Studio Express 11/08 includes MPI performance analysis capabilities and full OpenMP 3.0 compiler support. Learn about all this and the latest in Sun HPC ClusterTools 8.1.
Newsletters
Stay informed! Subscribe to HPCwire email Newsletters.
HPC Job Bank
-
HPC Systems Administrator
McGill University -
High Performance Computing Systems Administrator
Idaho National Laboratory -
Solution Engineer- HPC
Dell Inc -
Parallel Programmer
Cardiff University -
Principal Software Research Engineer
Indiana University -
Post Doctoral Researcher - Exascale Stream Computing
IBM - Visit the HPCwire Job Bank
Featured Events
-
July 13-16, 2009
WORLDCOMP'09
Las Vegas , NV
USA
-
August 24-28, 2009
Data Mining: Levels I, II, & III
Denver , CO
USA