HPCwire

The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing

HPCwire >> Off the Wire

LBNL, Tensilica Collaborate on Energy-Efficient Supercomputing


Page:  1  of  2
1 | 2   All  »  

SANTA CLARA, Calif., May 5 -- Tensilica, Inc. and the U.S. Department of Energy's Lawrence Berkeley National Laboratory today announced a collaboration program to explore new design concepts for energy-efficient high-performance scientific computer systems.

The joint effort is focused on novel processor and systems architectures using large numbers of small processor cores, connected together with optimized links, and tuned to the requirements of highly-parallel applications such as climate modeling. These demanding scientific problems require 100 to 1000 times higher computation throughput than today's high-end computing installations, but conventional systems require so much electricity, generate so much heat, and require such complex physical installations that the costs would be prohibitive. This collaboration in application-directed supercomputing aims at making "exascale systems" (up to one quintillion floating point operations per second) feasible and cost-effective.

The two organizations are well-suited for such a collaboration. Tensilica is the recognized leader in configurable processor technology and has become a leading provider of energy efficient processors for mobile audio and video applications. The Berkeley Lab Computing Sciences organization manages one of the world's leading supercomputing centers and has extensive experience in deploying leading-edge computer architectures to accelerate scientific discovery.

"Our studies show that energy costs make current approaches for supercomputing unsustainable," stated Horst Simon, Associate Laboratory Director, Computing Sciences for Berkeley Lab. "Hardware-software co-design using tiny processor cores, such as those made by Tensilica, holds great promise for systems that reduce power costs and increase practical system scale. Such processors, by their nature, must deliver maximum performance while consuming minimal power -- exactly the challenge facing the high performance computing community. One of the most compute-intensive applications is modeling global climate change, a critical research application and the perfect pilot application for energy-efficient computing optimization."

"Berkeley Lab is a world leader in providing supercomputing resources to support research across a wide range of disciplines, but their experience in climate modeling is especially well-suited for this project," stated Chris Rowen, Tensilica's president and CEO. "If we can better understand the factors influencing climate change -- and do so in a dramatically more energy-efficient way -- then we open the door for other breakthroughs. We are delighted to be able to contribute to this effort, applying Tensilica Xtensa processors and software to help solve a problem of global significance. The same ultra-efficient processor technology that powers cellular phones can now contribute to a breakthrough in energy-efficient scientific computing."

The team will use Tensilica's Xtensa LX extensible processor cores as the basic building blocks in a massively parallel system design. Each processor will dissipate a few hundred milliwatts of power, yet deliver billions of floating point operations per second and be programmable using standard programming languages and tools. This equates to an order-of-magnitude improvement in floating point operations per watt, compared to conventional desktop and server processor chips. The small size and low power of these processors allows tight integration at the chip, board and rack level and scaling to millions of processors within a power budget of a few megawatts.

The co-design effort will use automatic generation of processor designs, including simulation models, FPGA-based hardware implementation, and software tools to enable rapid prototyping and evaluation of processor instructions sets, interfaces, multi-processor communications mechanisms, and application enhancements.

The research effort also will address the challenges of optimizing memory and communication bandwidth to the massive array of processors, distribution of application functions across the array, and development of suitable prototyping and software development methods for large-scale application-optimized systems.

About Lawrence Berkeley National Laboratory

Lawrence Berkeley National Laboratory (Berkeley Lab) has been a leader in science and engineering research for more than 70 years, and holds the distinction of being the oldest of the U.S. Department of Energy's National Laboratories. The Lab manages a number of national user facilities, including the National Energy Research Scientific Computing Center (NERSC), which provides supercomputing resources to 2,900 users at national laboratories and universities. Managed by the University of California, Berkeley Lab conducts unclassified research across a wide range of scientific disciplines with key efforts in fundamental studies of the universe; quantitative biology; nanoscience; new energy systems and environmental solutions; and the use of integrated computing as a tool for discovery. For more information, go to www.lbl.gov.

Page:  1  of  2
1 | 2   All  »  

HPCwire on Twitter

Article Tools

  • Print This Page
  • Bookmark This Article

Share Options

(Digg, Technorati, more)


Subscribe

Discussion

There are 0 discussion items posted.  

HPC in the Cloud Part 2
People to Watch 2010


Feature Articles

The Week in Review

C-DAC announces plans for a petaflop system; IBM researchers are working on vertical integration techniques to extend Moore's Law another 15 years. We recap those stories and more in our weekly wrapup.
Read More...

Moscow State University Supercomputer Has Petaflop Aspirations

The Moscow State University supercomputer, Lomonosov, has been selected for a high-performance makeover, with the goal of tripling its processing power to achieve petaflop-level performance in 2010. T-Platforms, who developed and manufactured the supercomputer, is the odds-on favorite to lead the project.
Read More...

Intel Ups Performance Ante with Westmere Server Chips

Right on schedule, Intel has launched its Xeon 5600 processors, codenamed "Westmere EP." The 5600 represents the 32nm sequel to the Xeon 5500 (Nehalem EP) for dual-socket servers. Intel is touting better performance and energy efficiency, along with new security features, as the big selling points of the new Xeons.
Read More...

Top Headlines

Australia Commissions Cray Supercomputer

Mar 19 | OfficialWire | New super to support intelligence work Down Under. Read more...

Intel Partners See 'Easy' Upgrade Path With Xeon 5600 Chips

Mar 18 | ChannelWeb | Westmere parts already showing up in HPC machines. Read more...

AMD: OEMs primed for Opteron 6100s

Mar 17 | The Register | But what about the tier ones? Read more...

Arrival of the Desktop Supercomputer

Mar 17 | Cadalyst Magazine | A new generation of workstations is changing the nature of technical computing. Read more...

Scheduling HPC In The Cloud

Mar 17 | Linux Magazine | Latest iteration of Sun Grid Engine able to tap into Cloud. Read more...

Featured Whitepapers

Virtualization for Aggregation And The vSMP Architecture™

Jan 12 | | In-depth look at vSMP Foundation server virtualization technology, technical implementation, use cases and capabilities. The technical whitepaper provides an architectural overview and details on the three vSMP Foundation products: vSMP Foundation for SMP, vSMP Foundation for Cluster and vSMP Foundation for Cloud.

Copper Cable Technologies for High Performance Computing

Jan 18 | | This white paper discusses Gore’s copper cable assemblies, and how they continue to exceed the standards for providing reliable, cost-effective solutions for high-performance computer applications.

Multimedia

Webcast: Virtualized Data Center Roundtable

Join this online panel discussion for live Q&A with leading industry experts, analysts, and end-users to discuss the latest innovations, best practices, barriers to implementation, and measurable benefits of server virtualization with a particular focus on today's real world solutions.

Webcast: Watch SC09 Birds of a Feather Video: Scalable Fault-Tolerant HPC Supercomputers

Learn about scalable fault-tolerant architectures and examples of energy efficient and scalable supercomputing clusters using dual QDR InfiniBand to combine capacity computing with network failover capabilities with the help of programming languages such as MPI and a robust Linux cluster management package.

Webcast: High Performance Computing for a Smarter Planet

LIVE@SCO9: The IBM team discusses new innovations in hardware, software and services that help clients better understand their workloads and get insight from their R&D efforts. Technology demonstrations include the soon-to-be-released Power7 HPC processor, the DCS990 system with 2.4 petabytes of storage, the xCAT management tool, secure HPC cloud computing and more. Winners of two HPCwire Readers' and Editors’ Choice Awards! Take the IBM virtual tour at SC09 or more information go online to: http://www-03.ibm.com/systems/deepcomputing/sc09.html

SC09 HPC in the Cloud

Newsletters

Stay informed! Subscribe to HPCwire email Newsletters.






HPC Job Bank


Featured Events

HPC User Forum DICE
2010 High Performance Computing Linux Financial Markets
Cloud Computing Expo
Cloud Lab
ESC
DEISA PRACE Symposium