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<copyright>Copyright 2012, Tabor Communications</copyright>
<pubDate>Wed, 23 May 2012 23:33:36 EDT</pubDate>
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<title>NVIDIA Works On CPU Co-Dependency Issues with Kepler GPU</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-22/nvidia_works_on_cpu_co-dependency_issues_with_kepler_gpu.html</link>
<description>NVIDIA is telling everyone that the GK110, its new Kepler GPU aimed at supercomputing, is all about improving performance per watt. But the other driving theme behind the new architecture is reducing the GPU's reliance on its CPU host. How well it accomplishes both these goals areas could determine the success of the new chip in high performance computing.</description>
<pubDate>Tue, 22 May 2012 17:38:26 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-22/nvidia_works_on_cpu_co-dependency_issues_with_kepler_gpu.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
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<item>
<title>OpenACC Starts to Gather Developer Mindshare</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-17/openacc_starts_to_gather_developer_mindshare.html</link>
<description>PGI, Cray, and CAPS enterprise are moving quickly to get their new OpenACC-supported compilers into the hands of GPGPU developers. At NVIDIA's GPU Technology Conference this week, there was plenty of discussion around the new HPC accelerator framework, and all three OpenACC compiler makers, as well as NVIDIA, were talking up the technology.</description>
<pubDate>Thu, 17 May 2012 20:15:03 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-17/openacc_starts_to_gather_developer_mindshare.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
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<item>
<title>NVIDIA Launches Kepler Into HPC</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-15/nvidia_launches_kepler_into_hpc.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/Kepler_GPU_die_small.bmp" alt="" width="81" height="78" /&gt;NVIDIA has introduced its first Kepler-generation GPU product for high performance computing, and revealed some of the inner working of the new architecture. The announcement took place at the kickoff of the company's GPU Technology Conference taking place this week in San Jose, California.</description>
<pubDate>Tue, 15 May 2012 15:01:07 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-15/nvidia_launches_kepler_into_hpc.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
</item>
<item>
<title>Intel Rolls Out New Server CPUs</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-14/intel_rolls_out_new_server_cpus.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/Intel-Corp_small.jpg" alt="" width="90" height="65" /&gt;Intel Corp. has launched three new families of Xeon processors, joining the Xeon E5-2600 series the chipmaker introduced in March. These latest chips span the entire market for the Xeon line, from four- and two-socket servers, down to entry-level workstations and microservers. A number of HPC server makers, including SGI, Dell, and Appro announced updated hardware based on the new silicon.</description>
<pubDate>Mon, 14 May 2012 11:12:20 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-14/intel_rolls_out_new_server_cpus.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
</item>
<item>
<title>Novel Chip Technology to Power GRAPE-8 Supercomputer</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-10/novel_chip_technology_to_power_grape-8_supercomputer.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/eASIC_logo_small.jpg" alt="" width="108" height="34" /&gt;With the fastest supercomputers on the planet sporting multi-megawatt appetites, green HPC has become all the rage. The IBM Blue Gene/Q machine is currently number one in energy-efficient flops, but a new FPGA-like technology brought to market by semiconductor startup eASIC is providing an even greener computing solution. And one HPC project in Japan, known as GRAPE, is using the chips to power its newest supercomputer.</description>
<pubDate>Thu, 10 May 2012 20:47:34 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-10/novel_chip_technology_to_power_grape-8_supercomputer.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
</item>
<item>
<title>Myricom, Emulex Take Aim at High Performance Networking</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-09/myricom_emulex_take_aim_at_high_performance_networking.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/Myricom_Emulex.jpg" alt="" width="122" height="81" /&gt;Myricom and Emulex are teaming up to bring a series of network offerings to market targeted for high performance applications. The partnership will kick off with Emulex reselling Myricom 10GbE products into selected application domains, but the end game is to go after the high-flying InfiniBand market with products based on Emulex's Ethernet ASICs and Myricom's high performance software.</description>
<pubDate>Wed, 09 May 2012 15:58:03 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-09/myricom_emulex_take_aim_at_high_performance_networking.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
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<item>
<title>Thomas Sterling: 'I Think We Will Never Reach Zettaflops'</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-07/thomas_sterling:_i_think_we_will_never_reach_zettaflops_.html</link>
<description>&lt;img style="float: left;" src="http://media.hpcwire.com/images/Thomas_Sterling1.jpg" alt="" width="86" height="110" /&gt;As supercomputing makes its way through the petascale era, the future of the technology has never seemed so uncertain. HPC veteran Thomas Sterling takes us through some of the most critical developments in high performance computing, explaining why the transition to exascale is going to be very different than the ones in the past and how the United States is losing its leadership in HPC innovation.</description>
<pubDate>Mon, 07 May 2012 18:58:49 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-07/thomas_sterling:_i_think_we_will_never_reach_zettaflops_.html</guid>
<category>Feature</category>
</item>
<item>
<title>The Last Mile of Virtualization</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-03/the_last_mile_of_virtualization.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/exludus_logo.jpg" alt="" width="139" height="32" /&gt;The advent of multicore servers presents something of a challenge for application virtualization. This is especially true in the realm of high performance computing, an environment that has never been particularly friendly to virtualization. To overcome these hurdles, eXludus Technologies has introduced "micro-virtualization," a technology that brings virtualization down to the level of the core, and does so with minimal overhead.</description>
<pubDate>Thu, 03 May 2012 16:07:21 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-03/the_last_mile_of_virtualization.html</guid>
<category>Feature</category>
</item>
<item>
<title>TACC-Intel Symposium Highlights MIC Architecture Developments</title>
<link>http://www.hpcwire.com/hpcwire/2012-05-01/tacc-intel_symposium_highlights_mic_architecture_developments.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/knights_corner_small.JPG" alt="" width="108" height="91" /&gt;Researchers, hardware and software engineers, and high performance computing specialists from around the country attended the TACC-Intel Highly Parallel Computing Symposium last month at the Texas Advanced Computing Center (TACC). The meeting showcased the experiences of researchers who had ported their scientific computing codes to Intel&amp;rsquo;s Knights Ferry software development platform, as well as those working on the single-chip cloud (SCC).</description>
<pubDate>Tue, 01 May 2012 11:51:58 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-05-01/tacc-intel_symposium_highlights_mic_architecture_developments.html</guid>
<category>Feature</category>
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<item>
<title>Hot Interconnects Event Warms Up for Summer Meeting</title>
<link>http://www.hpcwire.com/hpcwire/2012-04-30/hot_interconnects_event_warms_up_for_summer_symposium.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/HOTI_logo.bmp" alt="" width="140" height="80" /&gt;This August, the IEEE is hosting its annual symposium on high-performance interconnects, known as Hot Interconnects. Now in its 20th year, the event focuses on the latest developments in the field with a special emphasis on how the technology is advancing in the realm of supercomputing and large-scale datacenters. The event covers both chip-to-chip interconnects as well as networking fabrics that bind whole systems and datacenters together.</description>
<pubDate>Mon, 30 Apr 2012 14:09:42 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-04-30/hot_interconnects_event_warms_up_for_summer_symposium.html</guid>
<category>Feature</category>
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<item>
<title>ESnet Launches Architecture to Help Researchers Deliver on Data-Intensive Science</title>
<link>http://www.hpcwire.com/hpcwire/2012-04-26/esnet_launches_architecture_to_help_researchers_deliver_on_data-intensive_science.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/ESnet_logo.jpg" alt="" width="114" height="119" /&gt;In order to help research institutions capitalize on the growing availability of high-bandwidth networks to manage their growing data sets, the DOE's Energy Sciences Network, known as ESnet, is working with the scientific community to encourage the use of a network design model called the &amp;ldquo;Science DMZ.&amp;rdquo; Leading the development of this effort is Eli Dart, a network engineer with previous experience at Sandia National Laboratories and the National Energy Research Scientific Computing Center. In this interview, Dart talks about the nature of the project and explains how such an architecture can help researchers.</description>
<pubDate>Thu, 26 Apr 2012 21:50:12 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-04-26/esnet_launches_architecture_to_help_researchers_deliver_on_data-intensive_science.html</guid>
<category>Feature</category>
</item>
<item>
<title>Intel Makes a Deal for Cray's Interconnect Assets</title>
<link>http://www.hpcwire.com/hpcwire/2012-04-25/intel_makes_a_deal_for_cray_s_interconnect_technology.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/Cray_Gemini_schematic_small.bmp" alt="" width="122" height="82" /&gt;Supercomputer maker Cray is methodically and inevitably shifting its technology focus from hardware to software. Another step in that direction played itself out this week in the company's sale of its highly treasured supercomputing interconnect technology. On Tuesday evening, Cray and Intel announced that they signed a "definitive agreement" that would send the interconnect program and expertise to the x86 chipmaker.</description>
<pubDate>Wed, 25 Apr 2012 22:29:01 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-04-25/intel_makes_a_deal_for_cray_s_interconnect_technology.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
</item>
<item>
<title>Some Thoughts on Intel’s Acquisition of Cray's Interconnect Technology</title>
<link>http://www.hpcwire.com/hpcwire/2012-04-25/some_thoughts_on_intel’s_acquistion_of_cray_s_interconnect_technology.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/Intel_Cray.JPG" alt="" width="91" height="77" /&gt;At first glance, the announced acquisition of Cray&amp;rsquo;s interconnect technology by Intel comes as a surprise to the HPC community, simply because Cray still stands for innovation, and with this deal they are selling one of their last proprietary assets. At second glance, however, you find a couple of good reasons, from the perspective of both parties, which makes it a win-win situation, at least in the short-term.</description>
<pubDate>Wed, 25 Apr 2012 14:46:08 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-04-25/some_thoughts_on_intel’s_acquistion_of_cray_s_interconnect_technology.html</guid>
<category>Feature</category>
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<item>
<title>Convey Cranks Up Performance with Latest FPGA-Accelerated Computer</title>
<link>http://www.hpcwire.com/hpcwire/2012-04-24/convey_cranks_up_performance_with_latest_fpga-accelerated_system.html</link>
<description>&lt;img style="float: left;" src="http://media2.hpcwire.com/hpcwire/Convey_HC-2.bmp" alt="" width="141" height="61" /&gt;Convey Computer has launched its newest x86-FPGA "hybrid-core" server. Dubbed HC-2, it represents the first major upgrade of the system since the company introduced the HC-1 product back in 2008. The new offering promises much better performance, but with a similar price range as the original system.</description>
<pubDate>Tue, 24 Apr 2012 15:53:20 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-04-24/convey_cranks_up_performance_with_latest_fpga-accelerated_system.html</guid>
<author>Michael Feldman</author>
<category>Feature</category>
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