<?xml version="1.0" encoding="utf-8"?><rss xmlns:atom="http://www.w3.org/2005/Atom" version="2.0">
<channel>
<atom:link type="application/rss+xml" rel="self" href="http://www.hpcwire.com/rss/hpcwire/visualization"/>
<title>HPC Wire: Visualization</title>
<link>http://www.hpcwire.com/</link>
<description/>
<copyright>Copyright 2012, Tabor Communications</copyright>
<pubDate>Wed, 23 May 2012 23:42:33 EDT</pubDate>
<lastBuildDate>Wed, 23 May 2012 23:42:33 EDT</lastBuildDate>
<generator>Xtenit</generator>
<docs>http://blogs.law.harvard.edu/tech/rss</docs>
<language>en-us</language>
<category>HPC Wire: Visualization</category>
<item>
<title>ANSYS Claims Faster Simulations with E5 Chips</title>
<link>http://www.hpcwire.com/hpcwire/2012-04-10/ansys_claims_faster_simulations_with_e5_chips.html</link>
<description>ANSYS software claims the increased throughput of Intel E5 processors has decreased simulation time and increased productivity. The company says it has worked with Intel in the lead up to the E5 launch, adding new features to their offering while improving performance. </description>
<pubDate>Tue, 10 Apr 2012 09:12:22 EDT</pubDate>
<guid>http://www.hpcwire.com/hpcwire/2012-04-10/ansys_claims_faster_simulations_with_e5_chips.html</guid>
<category>Off the Wire</category>
</item>
</channel>
</rss>

