HPCwire: Latest Benchmark Results on NEC Super Highlights SX-9 Performance

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November 19, 2008

Latest Benchmark Results on NEC Super Highlights SX-9 Performance

by John Boyd, Business and Technology Writer

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Researchers at Tohoku University in Sendai, north-eastern Japan, announced on Wednesday that they had broken a batch of performance records on their NEC SX-9 supercomputer, as measured on the HPC Challenge Benchmark test. Hiroaki Kobayashi, director the university's Cyberscience Center, said the SX-9 had achieved the highest marks ever in 19 of 28 areas the test evaluates in computer processing, memory bandwidth and networking bandwidth. The scores were matched against those previously achieved on the same independent benchmark test by other leading supercomputers, including IBM's Blue Gene/L, Cray's XT3/4 and SGI's Altix ICE, with the SX-9 coming out on top 64 percent of the time.

The news comes at a good time for NEC. The Tokyo-based manufacturer of vector-based supercomputers is battling in a market that has been moving away from its expensive high-performance vector processing models to systems that use more modestly priced commodity-type superscalar CPUs. These cheaper chips can be coupled tightly together or used in clusters of computers to achieve similar or better results than vector competitors -- at least in some areas of supercomputing.

At Tohoku University, however, a stronghold of vector computing since it installed its first SX-1 in 1985, Director Kobayashi argues that vector computing is essential for certain types of applications and will only increase in importance as advances are made in parallel processing.

"In the future, data parallel processing will become more important in high performance computing," says Kobayashi. "And vector processing provides a very efficient model for it." This is why, he adds, Intel, which has long provided short vector SIMD code extensions for its x86 architecture, is employing wider vector operations in its upcoming Larrabee graphics processing chip. "Regarding parallel processing, at the instruction-set level, vector instruction sets are the key to future processors, no matter what kind of micro-architecture is used," says Kobayashi."

In addition, he emphasizes that for the kind of programs that the 1,500 paying supercomputer users of the University's Cyberscience Center want to run, vector is still king. Most of these users are involved in government and academic research programs in areas like aerospace, environmental simulations, structural analysis and nanotechnology. "They want to conduct very large simulations, so are looking for an efficient handling mechanism to process extremely large amounts of data in a single operation," says Kobayashi. "Vector processing is best suited to this kind of application."

The SX-9 employs a single-chip vector processor capable of reaching 102 GFLOPS. Up to 16 CPUs sharing 1 TB of memory can be incorporated on a single node, combing to produce 1.6 TFLOPS of peak performance. The Tohoku University SX-9 set-up, which began operations this April, consists of 16 nodes, each of 16 CPUs, producing an overall peak performance of 26 TFLOPS. On a sustained performance bases, the Cyberscience Center's test results show a single SX-9 CPU outperforms that of the previous SX-8R by between four to eight times, depending on the application.

Much of the new CPU's improved performance can be accounted for by the addition of an arithmetic unit and raising the number of vector pipelines -- all integrated on a single chip that is the first to surpass 100 GFLOPS.

But Kobayashi notes that a new feature of the SX-9, the inclusion of an assignable data buffer or ADB, has also helped boost performance significantly. "ADB is software-controllable cache memory," he explains. "It lets the user assign the data to be cached, which prevents it from being evicted."

In a simulation used to detect the presence of land mines with electromagnetic waves, for instance, performance increased by 20 percent when ADB was used. In another simulation, which tracked the movement of tectonic plates (the cause of earthquakes), the use of ADB improved performance by 75 percent, while a simulation involving the physics of plasma under certain conditions saw performance jump two times when employing ADB.

Despite such gains, Kobayashi has a gripe with the current ADB design: the cache space is limited to just 256 kilobytes. This means users cannot place all the target data in the cache; rather, they must select only the portion that they judge will work most effectively in ADB. To determine the optimum amount of cache memory, the Cyberscience Center, which is developing a software simulator based on the SX-9 architecture to design future supercomputer models, ran simulations using real application code. To achieve the highest performance, the researchers found that a minimum of 8 MB of ADB memory is necessary. NEC has been so advised.

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