HPCwire: Mitrionics Looks Beyond FPGAs

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November 18, 2009

Mitrionics Looks Beyond FPGAs

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At SC09 this week, Mitrionics announced it has started to work on an experimental compiler that aims to make parallel programming architecture-agnostic. The goal of the work is to extend the Mitrion-C platform for FPGAs to multicore CPUs, cluster architectures, and eventually even GPGPUs. We asked Stefan Möhl, Mitrionics' chief science officer and co-founder, to explain what's behind the new technology and what prompted the decision to add support for other parallel architectures.

HPCwire: Can you tell us about the new programming capabilities of the Mitrionics platform that you announced here at the Supercomputing Conference?

Stefan Möhl: Well, we haven't added new programming capabilities to the Mitrionics' Accelerated Computing Platform yet. We are still in the proof-of-concept stage with this new compiler, but things look very promising. For this proof-of-concept compiler, the news is that existing Mitrion-C code, originally written for the MVP on FPGAs, will now also run on multicores and clusters. This initial proof-of-concept was made only to prove that the basic principles work, so there are limits to what code we can currently run. A production version of a portable programming language will require changes to Mitrion-C to make it less focused on what is needed for FPGA acceleration.

HPCwire: How does it work?

Möhl: The main challenge when porting between parallel architectures is that the level of granularity of the parallelism differs. For example, to parallelize code for vector processors, you would have to parallelize inner-most loops. To parallelize code for clusters, you would have to parallelize the outer-most loops. Doing general automatic parallelization (parallelization without re-writing the code) has not been solved, even after decades of research. Nor is there a general automatic way to transform one kind of parallelism into another.

Mitrion-C was originally developed as a programming language for the Mitrion Virtual Processor (MVP). The MVP is a hardware design for a compute engine specifically developed for high-performance execution in FPGAs. As such, it is full MIMD ((Multiple Instruction stream, Multiple Data stream) at the individual instruction level, so it potentially executes every single instruction of the program in parallel. This can be thought of as a limit-case for parallelism. Mitrion-C is a C-family language that supports and aids the programmer in specifying the kind of parallelism that the MVP requires. It is roughly as similar to ANSI-C as Java or C# are, so it isn't too unusual to use.

The trick that makes Mitrion-C work for parallel portability comes from an important asymmetry in parallelization. Though automatic parallelization without code re-writes is very hard to achieve, general automatic sequentialization is much, much easier. Trivially, operating systems have run multiple programs in parallel on sequential processors for many years. For efficient execution, there are of course many optimization considerations, but it is still much easier than automatic parallelization. This property is what we use to port Mitrion-C between platforms. Since the code is fully parallel from the start, we never parallelize at all, we only sequentialize. So for a cluster, instead of parallelizing outer-most loops, we sequentialize everything except the outer-most loops. And for a vector processor, we sequentialize everything except for the inner-most loops.

HPCwire: So if you don't have the parallelization problem, how can you handle the various memory architectures of multicore CPUs, GPGPUs and clusters, and so on?

Möhl: Our FPGA background has required us to consider these issues carefully from the start. FPGAs are usually connected to the system on data buses designed for devices with an order of magnitude less performance than FPGAs. So Mitrion-C was designed from the start to allow programmers to manage both memory latency and raw memory bandwidth in an effective manner. This issue will become increasingly important also for multicores and manycores, since increasing core counts without increasing clock-frequencies of data buses will put them in the same situation FPGAs have always been in.

Another important aspect comes from the diversity of FPGA cards. There are almost no two FPGA cards with the same memory sub-system, so we had to design Mitrion-C to have a memory model that addresses this from the start.

In Mitrion-C, there is no assumption of a single monolithic memory space. Instead, each collection may have its own address space, and different ones for different memory size and bandwidth requirements. This allows programmers to manually stage data from few, large and slow memories to many, small and fast memories in any number of levels. There are also several different built-in types for multi-dimensional data collections that let programmers specify what kind of access patterns a collection should permit. This helps the programmer in making correct and efficient programs, and also lets the compiler know what types of memory to place the data collection in. Of course, you can still write a program that requires more, larger or faster memories than a particular system has, but Mitrion-C will at least make you aware of what you demand of the system.

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Discussion

There are 1 discussion items posted.

Great Idea!
Submitted by mgollery on 11/19/2009 - 9:39AM

This is a great idea! Being able to generate files for GPGPU and FPGA from the same code base would be most excellent!

Post #1

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