HPCwire: NVIDIA Unleashes Fermi GPU for HPC

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November 15, 2009

NVIDIA Unleashes Fermi GPU for HPC

by Michael Feldman, HPCwire Editor

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NVIDIA has announced the first Fermi GPU products here at the Supercomputing Conference (SC09) in Portland, Oregon, where thousands of attendees will get a chance to see the company's next-generation chip in action. The GPUs will first touch down in NVIDIA's new Tesla 20-series products aimed at HPC workstations and servers. The company will be demonstrating the new hardware at its booth on the SC09 exhibition floor, starting on Tuesday.

For those of you who somehow missed the big Fermi unveiling in September, NVIDIA's latest GPU looks and acts much like a vector processor. The new architecture offers double-precision (DP) floating point performance north of 500 gigaflops per chip, systematic support for ECC memory, L1 and L2 caches, GDDR5 support, and a raft of new features to make the processor more programmer friendly, including C++ support. In short, Fermi is designed as a true computational GPU that is designed to offer a much wider application aperture for HPC, visual computing and data analytics than any previous graphics processor.

What they announced this week at SC09 were four Tesla 20 offerings -- the C2050 and C2070 for workstations, and the S2050 and S2070 for 1U servers. What follows are the specs the company is quoting today, but since the products won't hit the streets until next year, NVIDIA cautions that these numbers are "subject to change."

Unlike the Tesla 10-series, which came standard with 4 GB of on-board memory per GPU, the first 20-series products are offering two memory configurations. The x2050 models come with 3 GB per GPU (2.625 GB per GPU with ECC enabled), while the x2070 models double that to 6 GB per GPU (5.25 GB per GPU with ECC enabled). Local memory capacity is quite important to these devices since the new Teslas use the PCI Express bus to transfer data back and forth to the CPU. So to avoid the time-consuming data shuffling, it pays to have the entire data set the GPU is operating in its local memory.

NVIDIA is planning for volume deployment of the new Teslas starting in May 2010. That's probably later than the company would have preferred, given that there are plenty of users who would like to get their hands on them today. But with no equivalent technology in the HPC market, NVIDIA can afford to slip and slide a bit with the rollout. Fortunately, developers can get a jump start on their codes today. The CUDA C/C++ 3.0 beta, which incorporates Fermi support, is already available for download on NVIDIA's Web site.

When the new hardware does arrive, it will look much the same as the 10-series boards. As before, the workstation Teslas are populated with a single GPU, but because it's Fermi technology, they a deliver a lot more peak DP horsepower -- between 520 to 630 DP per chip. That means that a Dell or HP workstation, which can house two of these cards, can provide well over a teraflop. NVIDIA quotes typical power draw at 190W, with a maximum of 225W. That's a significant bump from the peak draw of the current C1060s at 187.8W, but since double precision performance is several times higher on the new parts, performance per watt is much improved.

The Tesla server boards contains four Fermi GPUs, and provide between 2.1 and 2.5 teraflops of DP -- pretty amazing figures for a 1U box. Again, there's a power penalty: 900W under a typical load, with a maximum of 1200W. That's roughly twice the power draw of a typical x86 dual-socket 1U server. However, since the fastest x86 server chips churn out roughly 100 peak gigaflops per CPU, a Tesla server is going to be about five times better in the performance per watt department.

GPUs have an additional advantage. Compared to a graphics memory, CPU memory tends to be much more bandwidth constrained, thus it is comparatively more difficult to extract all the theoretical FLOPS from the processor. This is one of the principal reasons that performance on data-intensive apps almost never scales linearly on multicore CPUs. GPU architectures, on the other hand, have always been designed as data throughput processors, so the FLOPS to bandwidth ratio is much more favorable.

Compared to a quad-core x86 CPU, application speedups of 10x -200x are fairly typical on the current generation 10-series. For example, using the C1060, users have demonstrated a 31x speedup for seismic processing, 83x for certain financial computing applications, and 17x on some molecular dynamics codes. Those numbers are bound to improve further once the Fermi-equipped Teslas are in the field.

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