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HPC in Underserved Regions: The Longest Last Mile
March 3, 2024
(Originally published in the Insight SoftMax blog Feb 27, 2024) Prior to the last Supercomputing23 conference in Denver, there was a pre-conference workshop Read more…
Cray Lays Out Vision for HPC-Big Data Convergence
December 3, 2015
Messaging around HPC-big data convergence which had been ramping up all year reached new heights at SC15 -- and you’d be hard-pressed to find a bigger cham Read more…
Danes Take Back Fastest Data Transfer Title
August 6, 2014
The team that broke the terabit barrier in 2009 is at it again. This time the High-Speed Optical Communications (HSOC) team at the Technical University of Denma Read more…
Is Amazon’s ‘Fast’ Interconnect Fast Enough for MPI?
April 10, 2013
Amazon's EC2 Cluster Compute instance goes head-to-head with Myrinet 10GigE cluster. Read more…
Stacking Stairs Against the Memory Wall
April 2, 2013
With ever-mounting CPU advancements that promise superior performance, the blame for lousy delivery on those chip promises lies squarely on memory. This problem isn’t just a matter of application performance—it’s also a matter of efficiency. This week Micron with partners Intel and others, including Altera, IBM, ARM, Xilinx and others..... Read more…
The Bandwidth Bottleneck
August 16, 2012
Lack of high bandwidth connectivity can severely hinder the use of cloud services for HPC workloads. Read more…
The Weekly Top Five – 05/26/2011
May 26, 2011
The Weekly Top Five features the five biggest HPC stories of the week, condensed for your reading pleasure. This week, we cover the NC State effort to overcome the memory limitations of multicore chips; the sale of the first-ever commercial quantum computing system; Cray's first GPU-accelerated machine; speedier machine learning algorithms; and the connection between shrinking budgets and increased reliance on modeling and simulation. Read more…
Terascale Memory Challenges and Solutions
December 6, 2010
In contrast to the previous decade, CPU clock rates are scaling slower over time due to the power constraints. However, the number of transistors per silicon area continue to increase roughly at the rate of Moore's Law. Therefore, CPUs are being designed and built with an increasing number of cores, with each core executing one or more threads of instructions. This puts a new kind of pressure on the memory subsystem. Read more…
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