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Managing Memory at Multicore

Sep 18, 2013 |

With the advance of multicore and manycore processors, managing caches becomes more difficult. Researchers at MIT suggest that it might make sense to let software, rather than hardware, manage these high-speed on-chip memory banks.

DOE Primes Pump for Exascale Supercomputers

Jul 12, 2012 |

I<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/computer_chips_on_die_small.jpg” alt=”” width=”102″ height=”93″ />ntel, AMD, NVIDIA, and Whamcloud have been awarded tens of millions of dollars by the US Department of Energy (DOE) to kick-start research and development required to build exascale supercomputers. The work will be performed under the FastForward program, a joint effort run by the DOE Office of Science and the National Nuclear Security Administration (NNSA) that will focus on developing future hardware and software technologies capable of supporting such machines.

Hybrid Memory Cube Angles for Exascale

Jul 10, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HMC_transparent.bmp” alt=”” width=”117″ height=”91″ />Computer memory is currently undergoing something of an identity crisis. For the past 8 years, multicore microprocessors have been creating a performance discontinuity, the so-called memory wall. It’s now fairly clear that this widening gap between compute and memory performance will not be solved with conventional DRAM products. But there is one technology under development that aims to close that gap, and its first use case will likely be in the ethereal realm of supercomputing.

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