Tag: DDR

Hybrid Memory Cube Angles for Exascale

Jul 10, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HMC_transparent.bmp” alt=”” width=”117″ height=”91″ />Computer memory is currently undergoing something of an identity crisis. For the past 8 years, multicore microprocessors have been creating a performance discontinuity, the so-called memory wall. It’s now fairly clear that this widening gap between compute and memory performance will not be solved with conventional DRAM products. But there is one technology under development that aims to close that gap, and its first use case will likely be in the ethereal realm of supercomputing.

Terascale Memory Challenges and Solutions

Dec 6, 2010 |

In contrast to the previous decade, CPU clock rates are scaling slower over time due to the power constraints. However, the number of transistors per silicon area continue to increase roughly at the rate of Moore’s Law. Therefore, CPUs are being designed and built with an increasing number of cores, with each core executing one or more threads of instructions. This puts a new kind of pressure on the memory subsystem.