With Moore’s law and associated silicon transistor performance “laws” winding down, there is renewed interest in accelerators, e.g., digital signal processors (DSPs), graphics processing units (GPUs), and field-programmable gate arrays (FPGAs). Measuring the peak floating-point performance of these non-traditional computing architectures is not without challenges, however. A new white paper from Altera’s Michael Parker attempts to shed Read more…
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/TI_ARM_DSP_SoC_small.bmp” alt=”” width=”90″ height=”94″ />NVIDIA, Intel and AMD were not the only chip vendors unveiling new HPC accelerators last week SC12. Texas Instruments (TI) announced a set of heterogeneous processors that they believe will offer among the best performance per watt in the industry. In this case, the chipmaker glued an ARM CPU and DSP together on the same die, offering a low-power SoC with an impressive number of FLOPS.
Spanish researcher uncovers plenty of flops per watt on TI’s latest silicon.
A funny thing happened on the way to 4G telecommunications. When Texas Instruments (TI) added floating point smarts to its new digital signal processor (DSP) to support the fourth-generation wireless standard, it found itself with a commercial chip that had some of the most impressive flops/watt performance on the planet. And that got some of the folks at TI wondering if they could parlay that into the ethereal world of high performance computing.