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Tag: exascale

DOE Supercomputing Aims for 100-200 PFLOPS in 2017

Jan 16, 2014 |

In a recent post on Atomic City Underground, Frank Munger examines the progress made by the CORAL project, which HPCwire detailed last year. CORAL – which stands for Collaboration of Oak Ridge, Argonne and Livermore – formed so that Oak Ridge National Laboratory (ORNL), Argonne (ANL) and Lawrence Livermore (LLNL) – could combine forces when Read more…

Japan Moves Forward with 2020 Exascale Plans

Jan 8, 2014 |

In the race to build the first exascale supercomputer, several nations have set their sites on 2020 as the make-or-break year. With six years to go until that deadline, we can expect exascale efforts to take on a new urgency. Japan, which is among the economic regions seeking exascale glory, just got a little closer Read more…

SC13 Spotlights Three Main Trends

Dec 18, 2013 |

Collecting my thoughts after a thrilling and enlightening Supercomputing Conference in Denver, I want to discuss some of the key trends and highlights observed. The annual conference is always a hotbed of product announcements and this year, the 25th running, was no exception. There are many articles covering the key announcements, so I instead want Read more…

Tackling the Power and Energy Wall for Future HPC Systems

Dec 17, 2013 |

As the cost of powering a supercomputer or a datacenter increases, next generation exascale systems need to be considerably more power- and energy-efficient than current supercomputers to be of practical use. Unlike petascale systems, where the primary concern was performance, exascale systems need to climb the power and energy walls in order to deliver sustainable exaflops performance. Pacifi c Northwest Laboratory (PNNL) researchers are exploring holistically energy and power efficiency aspects at all levels of granularity, from processor architecture to system integration.

HPC Progress: No More Free Lunch

Dec 11, 2013 |

As HPC news hits its end-of-year slump before the raft of new activity begins anew in January, what better time to take in some SC13 highlights that you may have missed. During the show, NVIDIA Corp. hosted a number of compelling booth sessions at its GPU Technology Theatre, and full videos of these talks are Read more…

Asia’s Place in the Exascale Pack

Dec 6, 2013 |

Efforts to field the first exascale supercomputer are currently in play by such nations as China, Japan, the US, and the EU. Not only would this achievement provide a powerful science and industry tool for the winning nation, there’s a substantial symbolic victory hanging in the balance. Over at Intel’s IT Peer Network blog, Victor Na, Read more…

SC13 Wrapup: Supercomputing’s Top Themes

Nov 24, 2013 |

For those of us who traveled to Denver for SC13, it’s now back to “normal” as the year in high performance computing begins its slow descent into relative silence before a fresh start in 2014. Sitting down to plow through the plethora of new items to pluck for a top announcements article seemed impossible without Read more…

Gordon Bell Prize Bubbles from Sequoia

Nov 22, 2013 |

Each year at SC, the ACM hands out one of the most coveted awards, the Gordon Bell Prize. The award, which became a regular feature of SC, began in 1987 and now carries a $10,000 prize sponsored by parallel computing luminary, Gordon Bell. Winners demonstrate high peak performance figures on real world applications or demonstrate Read more…

DOE Funds Exascale Interconnect R&D

Nov 15, 2013 |

The Department of Energy (DOE) continues to prime the R&D pump for the next-generation of supercomputers, exascale machines 50 times more powerful than today’s leading number-crunchers. In order to bring this goal to fruition, the Department of Energy’s Office of Science together with the National Nuclear Security Administration (NNSA) have awarded $25.4 million in research Read more…

Cool and Steady Wins the Exascale Race

Nov 12, 2013 |

Power, energy and reliability present major challenges to HPC researchers in their endeavor to build larger machines. As we approach the exascale era, both hardware and software designers need to account for these challenges while optimizing performance. The Parallel Programming Laboratory (PPL) at the University of Illinois at Urbana-Champaign (UIUC) has been actively working on Read more…