<img src=”http://media2.hpcwire.com/hpcwire/light-speed.gif” alt=”” width=”94″ height=”94″ />The Intelligence Advanced Research Projects Activity (IARPA) is putting out some RFI feelers in hopes of pushing new boundaries with an HPC program. However, at the core of their evaluation process is an overt dismissal of benchmarks, including floating operations per second (FLOPS).
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Gerhard_Wellein_small.jpg” alt=”” width=”95″ height=”85″ />At this June’s International Supercomputing Conference (ISC’13) in Leipzig, Germany, Gerhard Wellein will be delivering a keynote entitled, Fooling the Masses with Performance Results: Old Classics & Some New Ideas. HPCwire caught up with Wellein and asked him to preview some of the themes of his upcoming talk and expound on his philosophy of programming for performance in the multicore era.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Xeon_Phi_chip_small.jpg” alt=”” width=”96″ height=”79″ />With the recent introduction of Intel’s first Xeon Phi coprocessors, NVIDIA’s latest Kepler GPUs, and AMD’s new FirePro S10000 graphics cards, the competition for HPC chip componentry has entered a new phase. The three chipmakers have taken somewhat different paths, though, and it will be up to the market to decide which vendor’s approach will win the day.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Wallach_Intel_Core_i7_layout_small.bmp” alt=”” width=”100″ height=”62″ />As more “big data” applications make their way into HPC and commercial datacenters, system architects are reconsidering the fundamental designs of our computing machinery. In the first of a series of articles on HPC design, Convey chief scientist Steve Wallach talks about some of the defining architectural issues that span the new application landscape.
For new SDSC super, it’s all about the IOPS.