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Tag: Hybrid Memory Cube

Micron, Intel Reveal Memory Slice of Knight’s Landing

Jun 24, 2014 |

As we move into the pre-exascale era, issues of power consumption, network bandwidth, I/O and other issues will continue to push increasing integration. This was a key theme during the International Supercomputing Conference this week in Germany where Intel’s Raj Hazra provided an early look into how it will integrate various pieces of the future Read more…

Micron Exposes the Double Life of Memory with Automata Processor

Nov 22, 2013 |

If we had to take a pick from some of the most compelling announcements from SC13, the news from memory vendor (although that narrow distinction may soon change) Micron about its new Automata processor is at the top of the list. While at this point there’s still enough theory to lead us to file this Read more…

Stacking Stairs Against the Memory Wall

Apr 2, 2013 |

With ever-mounting CPU advancements that promise superior performance, the blame for lousy delivery on those chip promises lies squarely on memory. This problem isn’t just a matter of application performance—it’s also a matter of efficiency. This week Micron with partners Intel and others, including Altera, IBM, ARM, Xilinx and others…..

Micron Readies Hybrid Memory Cube for Debut

Jan 17, 2013 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HMC_side_view_SC12_small.jpg” alt=”” width=”95″ height=”85″ />The next-generation memory-maker Micron Technology was one of the many innovative companies demonstrating its wares on the Supercomputing Conference (SC12) show floor last November. Micron’s General Manager of Hybrid Technology Scott Graham was on hand to discuss the latest developments in their Hybrid Memory Cube (HMC) technology, a multi-chip module that aims to address one of the biggest challenges in high performance computing: scaling the memory wall.

Hybrid Memory Cube Angles for Exascale

Jul 10, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HMC_transparent.bmp” alt=”” width=”117″ height=”91″ />Computer memory is currently undergoing something of an identity crisis. For the past 8 years, multicore microprocessors have been creating a performance discontinuity, the so-called memory wall. It’s now fairly clear that this widening gap between compute and memory performance will not be solved with conventional DRAM products. But there is one technology under development that aims to close that gap, and its first use case will likely be in the ethereal realm of supercomputing.

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