Tag: Intel

Intel Launches ‘Knights Landing’ Phi Family for HPC, Machine Learning

Jun 21, 2016 |

From ISC 2016 in Frankfurt, Germany, this week, Intel Corp. announced that its new Xeon Phi product family, formerly code-named Knights Landing, is now shipping for high-performance computing and machine learning workloads. The company had been shipping to early customers for the last six months and was waiting to ramp up production before making the product generally available. The window also gave OEMs time to complete their readiness, said Intel’s Charlie Wuischpard.

HPE Tackles Phi, Debuts Mfg. Solution and New HPC Software Environment

Jun 20, 2016 |

Hewlett Packard Enterprise (HPE), now about eight months into its transition as a separate entity, retained the prestige of fielding the most systems of any vendor on the Top500 list announced at the ISC2016. HPE had 127 systems (25.4 percent) though the number was down from 155 just six months ago. Other ISC news included Read more…

What Knights Landing Is Not

Jun 18, 2016 |

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. I have found that everything is clear, when we really understand that Knights Landing is an Intel processor. That makes it NOT Knights Corner. Read more…

OpenACC Adds Support for OpenPOWER; Touts Growing Traction

Jun 13, 2016 |

In a show of strength leading up to ISC the OpenACC standards group today announced its first OpenPOWER implementation, the addition of three new members – University of Illinois, Brookhaven National Laboratory, and Stony Brook University – and details of its expanding 2016 training schedule. Michael Wolfe, technical director of OpenACC, also talked with HPCwire about thorny compiler challenges still remaining as…

Intel Xeon E7 Balloons In-memory Capacity, Targets Real-Time Analytics

Jun 8, 2016 |

Who crunches more data faster, wins. It’s this drive that cuts through and clarifies the essence of the evolutionary spirit in the computer industry, the dual desire to get to real time with bigger and bigger chunks of data. The locomotive: HPC technologies adapted to enterprise mission-critical data analytics. With its memory capacity of up Read more…

Exiting Intel, James Reinders Offers a Brief Personal Retrospective

Jun 6, 2016 |

You may have heard that Intel has encouraged “long timers” (like me) to consider early retirement. Well, the offer was convincing for me. After 10,001 days at Intel, it is time for me to start the next phase of my life. I’ve accepted the “ERP offer” (early retirement) with my last day being June 24, 2016 (exactly 10,000 days after my start date). I’ll be in the office as much as needed to help transitions and wrap things up. Let me know if you need/want anything from me as I finish up.

TACC Director Lays Out Details of 2nd-Gen Stampede System

Jun 2, 2016 |

With a $30 million award from the National Science Foundation announced today, the Texas Advanced Computing Center (TACC) at The University of Texas at Austin (UT Austin) will stand up a second-generation Stampede system based on Dell PowerEdge servers equipped with Intel “Knights Landing” processors, next-generation Xeon chips and future 3D XPoint memory.

Intel Announces New Knights Landing Book

May 30, 2016 |

“The fact is that Intel has aggressively decided to build a new kind of processor, which includes a number of advances that make it not only the most scalable processor the world has ever seen, but also one of the most versatile, configurable and highly integrated CPUs ever devised,” explains James Reinders as he describes Read more…

Lustre Takes Aim at Enterprise Security Requirements

May 23, 2016 |

“Security in Lustre reflects its roots as a high performance computing (HPC) file system,” said John Hammond of Intel’s High Performance Data Division. In traditional HPC deployments, Lustre resides in a physically secure and logically isolated environment, dependent on strict network access controls, managed by large and siloed teams focused on what’s happening with the systems, and accessed by users already holding appropriate clearances to log on and use the resources.

IBM Puts 3D XPoint on Notice with 3 Bits/Cell PCM Breakthrough

May 18, 2016 |

IBM scientists have broken new ground in the development of a phase change memory technology (PCM) that puts a target on competing 3D XPoint technology from Intel and Micron. IBM successfully stored 3 bits per cell in a 64k-cell array that had been pre-cycled 1 million times and exposed to temperatures up to 75∘C. A paper describing the advance was presented this week at the IEEE International Memory Workshop in Paris. Phase-change memory is an up-and-coming non-volatile memory technology…