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Micron, Intel Reveal Memory Slice of Knight’s Landing

Jun 24, 2014 |

As we move into the pre-exascale era, issues of power consumption, network bandwidth, I/O and other issues will continue to push increasing integration. This was a key theme during the International Supercomputing Conference this week in Germany where Intel’s Raj Hazra provided an early look into how it will integrate various pieces of the future Read more…

Russia to Develop Home-Grown Chips

Jun 23, 2014 |

Russian officials want to replace US microprocessors from Intel and AMD with locally-grown parts. According to recent reports from local news services, the Russian government is planning to create its own line of microprocessors using 64-bit ARM chips for use in governmental computers and servers. The new microprocessors will be designed by Baikal Electronics, a Read more…

NICS Tackles Big Science with Beacon

Jun 16, 2014 |

With support from the National Science Foundation and the University of Tennessee, Knoxville, the National Institute for Computational Science (NICS) is expanding access to Beacon, its newest HPC cluster, providing researchers with a powerful research tool. Efforts are underway to optimize a number of science and engineering applications for this system utilizing both Intel Xeon Read more…

Seismic Imaging at the DEEP End

Jun 3, 2014 |

With exascale presenting a much larger challenge than previous exponential computing markers, an integrated, collaborative approach is all the more necessary. While concerted funding efforts for extreme-scale computing came a bit later than many had hoped, there are several international efforts afoot currently, including the European project, DEEP. DEEP, which stands for Dynamical ExaScale Entry Read more…

Intel Gives Code Modernization Fresh Push

May 28, 2014 |

In the conversations leading up to exascale, one of the most frequently cited pain points is the need for massive software optimization and code modernization. But this isn’t just a relevant topic for the largest system operators at the supercomputing pinnacle. According to Intel’s General Manager of the Technical Computing Group, Charlie Wuischpard, there are Read more…

Intel True Scale Fabric – Made for HPC

May 26, 2014 |

Unlike today’s solid but somewhat stodgy basic enterprise computing, HPC tends to engender an enthusiasm and a fascination with the underlying technology that is unique to its practitioners. But there is a downside. An overemphasis on advanced feeds and speeds and the joys of parallelism can distract us from what is really key – what Read more…

35,000-Core Aussie Supercomputer to Feature ‘Haswell’ Chips

May 13, 2014 |

Western Australian research organization iVEC has revealed that its latest-generation Cray XC30 will be decked out with 35,000 Intel cores when a scheduled upgrade is completed later this year. According to the 2012 plan, Magnus, the phase 2 system installed at the Pawsey Centre in Perth, Western Australia, will employ a combination of Intel Ivy Bridge, Read more…

Talent Search Highlights Promising Flu Treatment

Apr 30, 2014 |

The last couple weeks have seen a number of student competitions showcasing some remarkably talented young people with an aptitude for HPC and science. Another student who has gained the recognition of the community and his peers via his scientific and computing prowess is Eric S. Chen, who last month took home first prize at Read more…

Emerging System Sets Stage for Exascale Science

Apr 29, 2014 |

Today we welcome a new large-scale system into the high performance computing fold with the formal announcement of Cori, a new supercomputer set to be installed at NERSC in the mid-2016 timeframe. Known in its RFP stages as NERSC-8, the new machine will sport over 9,300 nodes, featuring the next-generation Knights Landing architecture housed within Read more…

Benchmarking MPI Communication on Phi-Based Clusters

Mar 12, 2014 |

Intel’s Many Integrated Core (MIC) architecture was designed to accommodate highly-parallel applications, a great many of which rely on the Message Passing Interface (MPI) standard. Applications deployed on Intel Xeon Phi coprocessors may use offload programming, an approach similar to the CUDA framework for general purpose GPU (GPGPU) computing, in which the CPU-based application is Read more…