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Tag: Knight’s Corner

Intel Sheds Light on the “Corner to Landing” Leap

Dec 6, 2013 |

Since the first details about the MIC architecture emerged, Intel has continually harkened back to their vision of offering a high degree of parallelism inside a power efficient package that could promise programmability. With the eventual entry of the next generation Xeon Phi hitting the market in years to come with its (still unstated) high Read more…

Intel Brings Knights to the Roundtable at SC13

Nov 23, 2013 |

This week during SC13, Intel hosted a roundtable session to discuss the future of its upcoming Knights Landing product, hitting on where the key benefits are expected for technical computing users and how Knight’s Landing might influence the shape of next generation systems and applications. As Intel turns its focus on the Xeon front to Read more…

Intel Releases Knights Corner ISA, Lays Groundwork for MIC Launch

Jun 11, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”99″ height=”78″ />Intel has released a partial software stack for Knights Corner, the company’s first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor’s micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip.

TACC Steps Up to the MIC

Apr 21, 2011 |

Supercomputing center starts coding to Intel’s Many Integrated Core (MIC) chip.

Intel Charts Its Multicore and Manycore Future for HPC

Dec 1, 2010 |

As the high performance computing community hurtles toward the exaflop milestone, it has become clear that the natural evolution of multicore x86 CPUs won’t get the industry very far toward that goal. Manycore GPGPUs, on the other hand, do appear to be a viable path to exascale computing. So where does that leave GPU-less Intel?

Impressions of ISC 2010

Jun 3, 2010 |

Returning to ISC after a hiatus of several years and viewing the event from the vantage point of an industry analyst, the show appears to have made a quantum leap in terms of size and sophistication of the exhibit, and degree and intensity of business activity.

Intel Unveils Plans for HPC Coprocessor

Jun 1, 2010 |

Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.