Tag: manycore

Processor Diversity on the Rise, Reports Intersect360

Nov 12, 2015 |

Intel x86 processors continue to dominate HPC servers while the number of cores per processor also keeps rising, perhaps no surprises there. Also somewhat anticipated, the amount of memory per core, per processor, and per node is rising. These are the top line results of Intersect360 Research’s latest HPC sites survey on processor use. A Read more…

OpenACC Reviews Latest Developments and Future Plans

Nov 11, 2015 |

This week during the lead up to SC15 the OpenACC standards group announced several new developments including the release and ratification of the 2.5 version of the OpenACC API specification, member support for multiple new OpenACC targets, and other progress with the standard. “The 2.5 specification addresses an essential challenge of profiling code where a Read more…

Blacklisting Doesn’t Slow Intel Investment in China

Apr 28, 2015 |

Intel may be barred from selling leading edge technology to China’s top supercomputer sites but it is nonetheless ramping up its high-end collaboration with China. On April 21st, Intel launched the first Intel Parallel Computing Center in China, a joint effort with the Chinese Academy of Sciences (CAS), with widely publicized ceremonies in China. “This Read more…

A Comparison of Heterogeneous and Manycore Programming Models

Mar 2, 2015 |

The high performance computing (HPC) community is heading toward the era of exascale machines, expected to exhibit an unprecedented level of complexity and size. The community agrees that the biggest challenges to future application performance lie with efficient node-level execution that can use all the resources in the node. These nodes might be comprised of Read more…

Practical Advice for Knights Landing Coders

Feb 5, 2015 |

The National Energy Research Scientific Computing Center (NERSC) is on track to get its next supercomputer system, Cori, by mid-2016. While that’s more than a year away, it’s not too soon to start preparing for the new 30+ petaflops Cray machine, which will feature Intel’s next-generation Knights Landing architecture. So says Richard Gerber, Senior Science Read more…

Scalable Priority Queue Minimizes Contention

Feb 2, 2015 |

The multicore era has been in full-swing for a decade now, yet exploiting all that parallel goodness remains a prominent challenge. Ideally, compute efficiency would scale linearly with increased cores, but that’s not always the case. As core counts are only set to proliferate across the computing spectrum, it’s an issue that merits serious attention. Researchers from Read more…

Preparing for Manycore

Oct 13, 2014 |

One of several insightful presentations to come out of the DOE Computational Science Graduate Fellowship was delivered by Katie Antypas, Services Department Head, National Energy Research Scientific Computing Center, Lawrence Berkeley National Laboratory. In “Preparing Your Application for Advanced Manycore Architectures,” Antypas gives a humorous and on-point overview of major architectural trends in HPC and Read more…

NERSC Reveals 44 NESAP Code Teams

Sep 3, 2014 |

Last month the National Energy Research Scientific Computing Center (NERSC) announced a collaboration with supercomputing vendors Intel and Cray to prepare for Cori, the Cray XC supercomputer slated to be deployed at NERSC in 2016. To ensure that the highly diverse workloads of the DOE science community continue to be supported as over 5,000 users Read more…

Programmability Matters

Jun 30, 2014 |

While discussions of HPC architectures have long centered on performance gains, that is not the only measure of success, according to Petteri Laakso of Vector Fabrics. Spurred by ever-proliferating core counts, programmability is taking on new prominence. Vector Fabrics is a Netherlands-based company that specializes in multicore software parallelization tools, so programmability is high on Read more…

Managing Memory at Multicore

Sep 18, 2013 |

With the advance of multicore and manycore processors, managing caches becomes more difficult. Researchers at MIT suggest that it might make sense to let software, rather than hardware, manage these high-speed on-chip memory banks.