<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”83″ height=”63″ />On Monday at the International Supercomputing Conference in Hamburg, Intel announced that Knights Corner, the company’s first manycore product, would be in production before the end of 2012. The company also released a few more details about the upcoming product line, including the creation of a new Xeon brand for the architecture, some performance updates on pre-production silicon, and Cray’s adoption of MIC as part of its future Cascade supercomputer.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”99″ height=”78″ />Intel has released a partial software stack for Knights Corner, the company’s first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor’s micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_small.JPG” alt=”” width=”108″ height=”91″ />Researchers, hardware and software engineers, and high performance computing specialists from around the country attended the TACC-Intel Highly Parallel Computing Symposium last month at the Texas Advanced Computing Center (TACC). The meeting showcased the experiences of researchers who had ported their scientific computing codes to Intel’s Knights Ferry software development platform, as well as those working on the single-chip cloud (SCC).
The chipmaker hints its manycore coprocessor could find a home in the enterprise.
As processor core counts rise, MIT research suggests on-chip networks will be needed.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_small.JPG” alt=”” width=”105″ height=”87″ />As NVIDIA’s upcoming Kepler-grade Tesla GPU prepares to do battle with Intel’s Knight Corner, the companies are busy formulating their respective HPC accelerator stories. While NVIDIA has enjoyed the advantage of actually having products in the field to talk about, Intel has managed to capture the attention of some fence-sitters with assurances of high programmability, simple recompiles, and transparent scalability for its Many Integrated Core (MIC) coprocessors. But according to NVIDIA’s Steve Scott, such promises ignore certain hard truths about how accelerator-based computing really works.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HP_Corona_graphic.bmp” alt=”” width=”109″ height=”95″ />In high performance computing, Hewlett-Packard is best known for supplying bread-and-butter HPC systems, built with standard processors and interconnects. But the company’s research arm has been devising a manycore chipset, which would outrun the average-sized HPC cluster of today. The design represents a radical leap in performance, and if implemented, would fulfill the promise of exascale computing.
MIT’s Hornet simulator takes the sting out of manycore design.
The supercomputing biz seems to have shaken off most of the after-effects of the global recession, with scads of new deployments large and small around the world. China, in particular, continued its big push into HPC, notching its first home-grown super. And Japan ushered in the era of 10-petaflop supercomputing this year with its world-beating K Computer. But, as always, not all the HPC news was rosy. Here are the top hits and misses for the year.
In May, chip startup Adapteva debuted Epiphany, a manycore architecture designed to maximize floating point horsepower with the lowest possible energy footprint. The initial silicon was a 16-core processor, implemented on the 65nm process node. This week, the company announced it has taped out a 64-core version of the design on the 28nm process node, delivering 100 gigaflops of performance at under 2 watts of power.