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Intel Parts the Curtains on Xeon Phi… A Little Bit

Aug 28, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Xeon_Phi.jpg” alt=”” width=”120″ height=”91″ />As Intel’s Xeon Phi processor family gets ready to debut later this year, the chipmaker continues to reveal some of the details of its first manycore offering. Although the company isn’t yet ready to talk speeds and feeds, this week they did divulge some of their design decisions that they believe will make the Xeon Phi coprocessor shine as an HPC accelerator. The new revelations were presented on Tuesday at the IEEE-sponsored Hot Chips conference in Cupertino, California.

Tracking Xeon Phi’s Roots

Aug 6, 2012 |

Intel refines Knights Corner design as it prepares to go head-to-head against its GPU competition.

Intel Will Ship Knights Corner Chip in 2012

Jun 18, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”83″ height=”63″ />On Monday at the International Supercomputing Conference in Hamburg, Intel announced that Knights Corner, the company’s first manycore product, would be in production before the end of 2012. The company also released a few more details about the upcoming product line, including the creation of a new Xeon brand for the architecture, some performance updates on pre-production silicon, and Cray’s adoption of MIC as part of its future Cascade supercomputer.

Intel Releases Knights Corner ISA, Lays Groundwork for MIC Launch

Jun 11, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”99″ height=”78″ />Intel has released a partial software stack for Knights Corner, the company’s first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor’s micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip.

TACC-Intel Symposium Highlights MIC Architecture Developments

May 1, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_small.JPG” alt=”” width=”108″ height=”91″ />Researchers, hardware and software engineers, and high performance computing specialists from around the country attended the TACC-Intel Highly Parallel Computing Symposium last month at the Texas Advanced Computing Center (TACC). The meeting showcased the experiences of researchers who had ported their scientific computing codes to Intel’s Knights Ferry software development platform, as well as those working on the single-chip cloud (SCC).

Intel MIC for Business Applications?

Apr 17, 2012 |

The chipmaker hints its manycore coprocessor could find a home in the enterprise.

Hopping Off the Bus

Apr 12, 2012 |

As processor core counts rise, MIT research suggests on-chip networks will be needed.

NVIDIA Pokes Holes in Intel’s Manycore Story

Apr 3, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_small.JPG” alt=”” width=”105″ height=”87″ />As NVIDIA’s upcoming Kepler-grade Tesla GPU prepares to do battle with Intel’s Knight Corner, the companies are busy formulating their respective HPC accelerator stories. While NVIDIA has enjoyed the advantage of actually having products in the field to talk about, Intel has managed to capture the attention of some fence-sitters with assurances of high programmability, simple recompiles, and transparent scalability for its Many Integrated Core (MIC) coprocessors. But according to NVIDIA’s Steve Scott, such promises ignore certain hard truths about how accelerator-based computing really works.

HP Scientists Envision 10-Teraflop Manycore Chip

Mar 15, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HP_Corona_graphic.bmp” alt=”” width=”109″ height=”95″ />In high performance computing, Hewlett-Packard is best known for supplying bread-and-butter HPC systems, built with standard processors and interconnects. But the company’s research arm has been devising a manycore chipset, which would outrun the average-sized HPC cluster of today. The design represents a radical leap in performance, and if implemented, would fulfill the promise of exascale computing.

Chip Simulation for the 1000-Core Era

Mar 6, 2012 |

MIT’s Hornet simulator takes the sting out of manycore design.

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