Tag: manycore

Programming the Xeon Phi

Dec 12, 2012 |

Intel’s manycore wonder comes with its own programming challenges.

Intel Brings Manycore x86 to Market with Knights Corner

Nov 12, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”98″ height=”85″ />Intel Corp. officially made its entry into the manycore realm today as it debuted “Knights Corner,” the company’s first Xeon Phi coprocessor. The new products clock in at just over a teraflop, double precision, setting the stage for an HPC accelerator battle that will pit Intel against GPU makers NVIDIA and AMD. Both of those companies also released their latest HPC accelerators into the wild earlier today at the annual Supercomputing Conference in Salt Lake City.

Intel Updates Plans for 48-Core Chip

Nov 1, 2012 |

What could you do with a 48-core smart phone? If Intel has its way, you won’t have to wait long to find out.

Adapteva Reaches Funding Goal for Parallella Project

Oct 29, 2012 |

Kickstarter investment model notches another high-tech success.

Adapteva Launches Crowd-Source Funding for Its Floating Point Accelerator

Sep 28, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Epiphany_16_small.JPG” alt=”” width=”93″ height=”79″ />Chipmaker Adapteva is attempting to bypass the conventional venture capital funding route and collect money via a micro-investor platform known as Kickstarter. In the process, the company will open up its software and hardware design for its manycore Epiphany architecture, and deliver a parallel computing kit to anyone who can ante up $99.

HP, Intel Score Petaflop Supercomputer at DOE Lab

Sep 5, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/NREL_logo.gif” alt=”” width=”112″ height=”48″ />The US Department of Energy’s National Renewable Energy Laboratory (NREL) has ordered a $10 million HP supercomputer equipped with the latest Intel Xeon CPUs and Xeon Phi coprocessors. When completed in 2013, the system will deliver one petaflop of performance and will take up residence in one of the most energy-efficient datacenters in the world.

Intel Parts the Curtains on Xeon Phi… A Little Bit

Aug 28, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Xeon_Phi.jpg” alt=”” width=”120″ height=”91″ />As Intel’s Xeon Phi processor family gets ready to debut later this year, the chipmaker continues to reveal some of the details of its first manycore offering. Although the company isn’t yet ready to talk speeds and feeds, this week they did divulge some of their design decisions that they believe will make the Xeon Phi coprocessor shine as an HPC accelerator. The new revelations were presented on Tuesday at the IEEE-sponsored Hot Chips conference in Cupertino, California.

Tracking Xeon Phi’s Roots

Aug 6, 2012 |

Intel refines Knights Corner design as it prepares to go head-to-head against its GPU competition.

Intel Will Ship Knights Corner Chip in 2012

Jun 18, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”83″ height=”63″ />On Monday at the International Supercomputing Conference in Hamburg, Intel announced that Knights Corner, the company’s first manycore product, would be in production before the end of 2012. The company also released a few more details about the upcoming product line, including the creation of a new Xeon brand for the architecture, some performance updates on pre-production silicon, and Cray’s adoption of MIC as part of its future Cascade supercomputer.

Intel Releases Knights Corner ISA, Lays Groundwork for MIC Launch

Jun 11, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”99″ height=”78″ />Intel has released a partial software stack for Knights Corner, the company’s first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor’s micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip.