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Terascale Memory Challenges and Solutions

Dec 6, 2010 |

In contrast to the previous decade, CPU clock rates are scaling slower over time due to the power constraints. However, the number of transistors per silicon area continue to increase roughly at the rate of Moore’s Law. Therefore, CPUs are being designed and built with an increasing number of cores, with each core executing one or more threads of instructions. This puts a new kind of pressure on the memory subsystem.

Violin Punts Flash-Mem Array with ’10X Performance Advantage’

May 25, 2010 |

Company claims speed and cost advantages over rivals’ flash arrays.