Tag: memory

Micron Steers Roadmap Around Memory Scaling Obstacles

Aug 27, 2015 |

In a packed session at IDF 2015 in San Francisco last week, Scott Graham, Micron’s general manager of Hybrid Memory, discussed some of the key themes occurring in the memory landscape from Micron’s perspective. “It’s an exciting time in the industry and there’s a lot going on with memory development in system architecture and software Read more…

HP Removes Memristors from Its ‘Machine’ Roadmap Until Further Notice

Jun 11, 2015 |

One year after Hewlett-Packard launched its ambitious “this will change everything” project called “The Machine,” the company is making some concessions to its initial vision, something it says is necessary in order to deliver a working prototype by next year. Announced with great fanfare at last year’s HP Discovery event, the Machine was to be Read more…

ISC 2015 Keynoter Thomas Sterling on Memory in HPC

Apr 15, 2015 |

The Wednesday keynote at this year’s ISC High Performance conference by HPC veteran Dr. Thomas Sterling promises to be an enlightening and lively presentation of the HPC year in review. And if previous years are a guide, Dr. Sterling will deliver it with the unique humor and style that has become his trademark. The late Read more…

Micron Reveals HPC Ambitions with Convey Purchase

Apr 1, 2015 |

If you’re looking to establish yourself as an HPC player, you can either develop the technology yourself or purchase an established HPC company. Today, advanced memory maker Micron went with the latter course of action by acquiring Convey Computer Corp, widely known for its deep HPC roots and track record delivering hybrid-core computing. The financial terms Read more…

Co-designing for Big Data in Barcelona

Feb 12, 2015 |

The third annual Big Data and Extreme Computing conference gathered in Barcelona last month, bringing more than 100 experts from around the world together to report on ground-breaking research at the intersection of big compute and big data. As with last year, the event played host to a wide-range of relevant and timely presentations, including Read more…

Japan Concludes Exascale Feasibility Study

Dec 3, 2014 |

One of the leading contenders in the race to establish an exascale supercomputer has published the results of a feasibility study began in 2012, exploring ways to achieve high-bandwidth sufficient for coming memory-intensive applications. Japan’s Feasibility Study of Future HPCI (High Performance Computing Infrastructure) systems, launched by MEXT (Ministry of Education, Culture, Sports, Science and Technology), set out with Read more…

Micron, Intel Reveal Memory Slice of Knight’s Landing

Jun 24, 2014 |

As we move into the pre-exascale era, issues of power consumption, network bandwidth, I/O and other issues will continue to push increasing integration. This was a key theme during the International Supercomputing Conference this week in Germany where Intel’s Raj Hazra provided an early look into how it will integrate various pieces of the future Read more…

Intel Brings Knights to the Roundtable at SC13

Nov 23, 2013 |

This week during SC13, Intel hosted a roundtable session to discuss the future of its upcoming Knights Landing product, hitting on where the key benefits are expected for technical computing users and how Knight’s Landing might influence the shape of next generation systems and applications. As Intel turns its focus on the Xeon front to Read more…

Micron Exposes the Double Life of Memory with Automata Processor

Nov 22, 2013 |

If we had to take a pick from some of the most compelling announcements from SC13, the news from memory vendor (although that narrow distinction may soon change) Micron about its new Automata processor is at the top of the list. While at this point there’s still enough theory to lead us to file this Read more…

Managing Memory at Multicore

Sep 18, 2013 |

With the advance of multicore and manycore processors, managing caches becomes more difficult. Researchers at MIT suggest that it might make sense to let software, rather than hardware, manage these high-speed on-chip memory banks.

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