Traditional HPC languages, Fortran, C and C++, have little native control over hardware capabilities such as SIMD operations, multi-core availability and prefetch instructions. The burden of optimization is therefore…
<img src=”http://media2.hpcwire.com/hpcwire/test_tube_image_200x.jpg” alt=”” width=”93″ height=”61″ />The top research stories of the week include the 2012 Turing Prize winners; an examination of MIC acceleration in short-range molecular dynamics simulations; a new computer model to help predict the best HIV treatment; the role of atmospheric clouds in climate change models; and more reliable HPC cloud computing.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_small.JPG” alt=”” width=”108″ height=”91″ />Researchers, hardware and software engineers, and high performance computing specialists from around the country attended the TACC-Intel Highly Parallel Computing Symposium last month at the Texas Advanced Computing Center (TACC). The meeting showcased the experiences of researchers who had ported their scientific computing codes to Intel’s Knights Ferry software development platform, as well as those working on the single-chip cloud (SCC).
The Texas Advanced Computing Center (TACC) has revealed plans to deploy a cutting-edge petascale supercomputer courtesy of a $27.5 million dollar NSF award. Built by Dell, the system will consist of 2 petaflops of Sandy Bridge-EP processors accelerated by an additional 8 petaflops of Intel’s Many Integrated Core (MIC) coprocessors. The machine is scheduled to boot up in late 2012 and be ready for production in January 2013.
Manycore MIC coprocessors beat out GPUs in future NSF-funded supercomputer.
According to Intel, its Xeon will remain the cloud hardware choice in the near term.
Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.