We’ve scoured the journals and conference proceedings to bring you the top research stories of the week. This diverse set of items includes the latest CAREER award recipient; the push to bring parallel computing to the classroom; HPC in accelerator science; the emerging Many-Task Computing paradigm; and a unified programming model for data-intensive computing.
The top research stories of the week include an evaluation of multi-stage programming with Terra; a look at parallel I/O for multicore architectures; a survey of on-chip monitoring approaches used in multicore SoCs; a review of grid security protocols and architectures; and a discussion of the finer distinctions between HPC and cloud computing.
<img src=”http://media2.hpcwire.com/hpccloud/cloud_graphic_150x.jpg” alt=”” width=”94″ height=”81″ />Our top HPC cloud research story this week lays out a lightweight approach to implementing virtual machine monitors. Other items explore an innovative parallel cloud storage system, HPC-to-cloud migration, anywhere-anytime cluster monitoring, and a framework for cloud storage.
<img src=”http://media2.hpcwire.com/hpcwire/world_connectivity_200x.jpg” alt=”” width=”95″ height=”70″ />The top research stories of the week include lessons learned from system failures; a cross-platform OpenCL implementation; the best memory to extract GPU’s potential; innovative ideas for next-generation interconnects; and the benefits of cloud storage to HPC applications.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Gerhard_Wellein_small.jpg” alt=”” width=”95″ height=”85″ />At this June’s International Supercomputing Conference (ISC’13) in Leipzig, Germany, Gerhard Wellein will be delivering a keynote entitled, Fooling the Masses with Performance Results: Old Classics & Some New Ideas. HPCwire caught up with Wellein and asked him to preview some of the themes of his upcoming talk and expound on his philosophy of programming for performance in the multicore era.
What could you do with a 48-core smart phone? If Intel has its way, you won’t have to wait long to find out.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/exludus_logo.jpg” alt=”” width=”139″ height=”32″ />The advent of multicore servers presents something of a challenge for application virtualization. This is especially true in the realm of high performance computing, an environment that has never been particularly friendly to virtualization. To overcome these hurdles, eXludus Technologies has introduced “micro-virtualization,” a technology that brings virtualization down to the level of the core, and does so with minimal overhead.
As processor core counts rise, MIT research suggests on-chip networks will be needed.
MIT’s Hornet simulator takes the sting out of manycore design.