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TACC-Intel Symposium Highlights MIC Architecture Developments

May 1, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_small.JPG” alt=”” width=”108″ height=”91″ />Researchers, hardware and software engineers, and high performance computing specialists from around the country attended the TACC-Intel Highly Parallel Computing Symposium last month at the Texas Advanced Computing Center (TACC). The meeting showcased the experiences of researchers who had ported their scientific computing codes to Intel’s Knights Ferry software development platform, as well as those working on the single-chip cloud (SCC).

Intel MIC for Business Applications?

Apr 17, 2012 |

The chipmaker hints its manycore coprocessor could find a home in the enterprise.

Hopping Off the Bus

Apr 12, 2012 |

As processor core counts rise, MIT research suggests on-chip networks will be needed.

The Processors of Petascale

Apr 10, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Sandy-Bridge_EP_small.jpg” alt=”” width=”109″ height=”91″ />While the supercomputing digerati argue about what an exascale machine will look like at the end of this decade, recent history suggests that there will be a healthy diversity of designs, at least with regard to processor architecture. As of this week, there are 20 known petascale systems deployed, which in aggregate encompass five different varieties of microprocessors. And that level of diversity shows no signs of reversing itself.

Intel Releases Sandy Bridge Server CPUs Into the Wild

Mar 7, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Sandy-Bridge_EP_small.jpg” alt=”” width=”98″ height=”90″ />Intel officially launched its new Xeon E5-2600 processor family on Tuesday, months after the chips had been deployed in supercomputers at several major HPC sites around the world. The new CPU represents the company’s latest Xeon offering for dual-socket servers, and boasts a number of new features including better performance, a new floating point instruction set in AVX, and integrated I/O.

China’s Dark Horse Supercomputing Chip: FeiTeng

Jan 19, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/FT64_chip.bmp” alt=”” width=”81″ height=”71″ />Chinese development of domestic microprocessors for high performance computing seems to be ramping up. The Godson-3B and ShenWei SW1600 CPUs were the first out of the gate, with the latter chip powering a Chinese petascale supercomputer. Waiting in the wings is the FeiTeng processor, an architecture that could be the one that takes Chinese supercomputing into the exascale realm.

Adapteva Builds Manycore Processor That Will Deliver 70 Gigaflops/Watt

Oct 3, 2011 |

In May, chip startup Adapteva debuted Epiphany, a manycore architecture designed to maximize floating point horsepower with the lowest possible energy footprint. The initial silicon was a 16-core processor, implemented on the 65nm process node. This week, the company announced it has taped out a 64-core version of the design on the 28nm process node, delivering 100 gigaflops of performance at under 2 watts of power.

NVIDIA Revs Up Tesla GPU

May 17, 2011 |

GPU maker NVIDIA has ratcheted up the core count and clock speed on its Tesla GPU processor. The new M2090 module for servers delivers 665 double precision gigaflops, representing close to a 30 percent increase over the previous generation Tesla part. The memory bandwidth on the device was bumped up as well, from 150 GB/second to 178 GB/second. The new GPU boosts performance significantly across a number of HPC codes.

China Makes Its Own Supercomputing Cores

Mar 7, 2011 |

New crop of Chinese supercomputers will feature homegrown chips.

AMD Lifts Curtain on Bulldozer Design Specs

Feb 23, 2011 |

Details of AMD’s upcoming Bulldozer chip revealed.