NVIDIA’s CUDA is easily the most popular programming language for general-purpose GPU computing. But one of the more interesting developments in the CUDA-verse doesn’t really involve GPUs at all. In September, HPC compiler vendor PGI (The Portland Group Inc.) announced its intent to build a CUDA compiler for x86 platforms. The technology will be demonstrated for the first time in public at SC10 this week in New Orleans.
In an HPC market that seems determined to go down the CPU-GPU path, upstart Convey Computer may yet offer a few surprises. The company today unveiled the sequel to its HC-1 platform it introduced in 2008. Called the HC-1ex, the new system adds a lot more performance and capability, but retains the original x86-FPGA co-processor design.
Big Blue sees green in mainstream high performance computing market.
Although 2010 still has a few months left to go, the competition in the x86 server processor arena for 2011 is already setting up to be a knock-down, drag-out fight. Both AMD and Intel are introducing new high-end server chips with revamped microarchitectures next year, and, at the same time, upping the core counts over their previous generation products.
Advanced Micro Devices is hoping Bulldozer, the company’s first x86 microarchitecture redesign in seven years, will bring back the glory days for the Opteron. AMD revealed additional details about the new architecture this week during the Hot Chips conference at Stanford University.
ARM chips for servers and design of 16-core Godson CPU will also be presented at August conference.
Westmere EX server chip will support 20 threads.
History provides some hints on how the CPU-GPU dynamic might play out.
At last week’s International Supercomputing Conference (ISC) in Hamburg, HPCwire sat down with Cray CTO Steve Scott to talk about life after Baker, where he revealed the company’s plans for its upcoming “Cascade” supercomputer and how the exascale landscape is shaping up.
Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.