Big Blue sees green in mainstream high performance computing market.
Although 2010 still has a few months left to go, the competition in the x86 server processor arena for 2011 is already setting up to be a knock-down, drag-out fight. Both AMD and Intel are introducing new high-end server chips with revamped microarchitectures next year, and, at the same time, upping the core counts over their previous generation products.
Advanced Micro Devices is hoping Bulldozer, the company’s first x86 microarchitecture redesign in seven years, will bring back the glory days for the Opteron. AMD revealed additional details about the new architecture this week during the Hot Chips conference at Stanford University.
ARM chips for servers and design of 16-core Godson CPU will also be presented at August conference.
Westmere EX server chip will support 20 threads.
History provides some hints on how the CPU-GPU dynamic might play out.
At last week’s International Supercomputing Conference (ISC) in Hamburg, HPCwire sat down with Cray CTO Steve Scott to talk about life after Baker, where he revealed the company’s plans for its upcoming “Cascade” supercomputer and how the exascale landscape is shaping up.
Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.
SGI has upgraded its HPC blade server lineup with the latest x86 silicon and a turbo-charged InfiniBand network. The Altix ICE 8400 is the successor to the company’s 8200 series and is designed as a premier solution for the HPC cluster market, scaling as high as 64,000 nodes.
Nehalem EX eliminates many of the traditional weak spots of the x86 architecture.