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Tag: Xeon

Haswell Speeds Popular Financial App

Sep 17, 2014 |

Continuing our coverage of the new Intel “Haswell” Xeon E5 v3 series chips, we turn our attention to a recent blog post from software acceleration specialists Xcelerit to see how the Haswell fares on a popular Monte-Carlo financial application. The Haswell E5 family offers significant performance gains over the previous Ivy Bridge processors but to Read more…

Haswell-EP Performance Deep Dive

Sep 16, 2014 |

A recent Microway blog post offers a detailed look at how the new Intel Xeon E5-2600v3 “Haswell-EP” processors perform for HPC applications. “The Xeon E5-2600v3 processors introduce the highest performance available to date in a socketed CPU. For the first time, a single CPU is capable of more than half a TeraFLOPS (500 GFLOPS),” notes Read more…

New Haswells Spark Open Season for HPC Systems

Sep 15, 2014 |

What do you get when you add more cores, improved memory bandwidth, and a notable uptick in performance out of a freshly-launched chip? One hell of a lot of announcements from a broad, hungry base of server makers. And to be fair, a lot of excitement from the HPC user community to boot. While one Read more…

Intel ‘Haswell’ Xeon E5s Aimed Squarely at HPC

Sep 8, 2014 |

The HPC market is a key one for Intel’s Xeon E5 family of processors, and that is perfectly evident as the chip maker rolls out the “Haswell” Xeon E5-2600 v3 processors for servers and workstations at its Intel Developer Forum today in San Francisco. Many of the new features in the Haswell Xeon E5s are Read more…

35,000-Core Aussie Supercomputer to Feature ‘Haswell’ Chips

May 13, 2014 |

Western Australian research organization iVEC has revealed that its latest-generation Cray XC30 will be decked out with 35,000 Intel cores when a scheduled upgrade is completed later this year. According to the 2012 plan, Magnus, the phase 2 system installed at the Pawsey Centre in Perth, Western Australia, will employ a combination of Intel Ivy Bridge, Read more…

Benchmarking MPI Communication on Phi-Based Clusters

Mar 12, 2014 |

Intel’s Many Integrated Core (MIC) architecture was designed to accommodate highly-parallel applications, a great many of which rely on the Message Passing Interface (MPI) standard. Applications deployed on Intel Xeon Phi coprocessors may use offload programming, an approach similar to the CUDA framework for general purpose GPU (GPGPU) computing, in which the CPU-based application is Read more…

Intel Sheds Light on the ‘Corner to Landing’ Leap

Dec 6, 2013 |

Since the first details about the MIC architecture emerged, Intel has continually harkened back to their vision of offering a high degree of parallelism inside a power efficient package that could promise programmability. With the eventual entry of the next generation Xeon Phi hitting the market in years to come with its (still unstated) high Read more…

Intel Brings Knights to the Roundtable at SC13

Nov 23, 2013 |

This week during SC13, Intel hosted a roundtable session to discuss the future of its upcoming Knights Landing product, hitting on where the key benefits are expected for technical computing users and how Knight’s Landing might influence the shape of next generation systems and applications. As Intel turns its focus on the Xeon front to Read more…

Full Details Uncovered on Chinese Top Supercomputer

Jun 2, 2013 |

With help from a draft report from Jack Dongarra of the University of Tennessee and Oak Ridge National Laboratory, who also spearheads the process of verifying the top of the pack super, we are able to share the full processor, Xeon Phi coprocessor, custom interconnect, storage and memory, as well as power and cooling information. The supercomputer out of China will be…

The Week in HPC Research

Mar 21, 2013 |

<img src=”http://media2.hpcwire.com/hpcwire/Cloud_Storage_and_Bioinformatics_in_a_private_cloud_Fig._3_150x.png” alt=”” width=”95″ height=”95″ />The top research stories of the week include an evaluation of sparse matrix multiplication performance on Xeon Phi versus four other architectures; a survey of HPC energy efficiency; performance modeling of OpenMP, MPI and hybrid scientific applications using weak scaling; an exploration of anywhere, anytime cluster monitoring; and a framework for data-intensive cloud storage.