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Tag: Xeon

Benchmarking MPI Communication on Phi-Based Clusters

Mar 12, 2014 |

Intel’s Many Integrated Core (MIC) architecture was designed to accommodate highly-parallel applications, a great many of which rely on the Message Passing Interface (MPI) standard. Applications deployed on Intel Xeon Phi coprocessors may use offload programming, an approach similar to the CUDA framework for general purpose GPU (GPGPU) computing, in which the CPU-based application is Read more…

Intel Brings Knights to the Roundtable at SC13

Nov 23, 2013 |

This week during SC13, Intel hosted a roundtable session to discuss the future of its upcoming Knights Landing product, hitting on where the key benefits are expected for technical computing users and how Knight’s Landing might influence the shape of next generation systems and applications. As Intel turns its focus on the Xeon front to Read more…

Full Details Uncovered on Chinese Top Supercomputer

Jun 2, 2013 |

With help from a draft report from Jack Dongarra of the University of Tennessee and Oak Ridge National Laboratory, who also spearheads the process of verifying the top of the pack super, we are able to share the full processor, Xeon Phi coprocessor, custom interconnect, storage and memory, as well as power and cooling information. The supercomputer out of China will be…

The Week in HPC Research

Mar 21, 2013 |

<img src=”http://media2.hpcwire.com/hpcwire/Cloud_Storage_and_Bioinformatics_in_a_private_cloud_Fig._3_150x.png” alt=”" width=”95″ height=”95″ />The top research stories of the week include an evaluation of sparse matrix multiplication performance on Xeon Phi versus four other architectures; a survey of HPC energy efficiency; performance modeling of OpenMP, MPI and hybrid scientific applications using weak scaling; an exploration of anywhere, anytime cluster monitoring; and a framework for data-intensive cloud storage.

Intel Xeon Phi Versus ‘Sandy Bridge’

Mar 5, 2013 |

How does the Phi coprocessor measure up to Xeon “Sandy Bridge” brand-mate?

Adaptive Revs Moab, Debuts Remote Virtualization Edition

Nov 28, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpccloud/Adaptive_Computing_Moab_2012.jpg” alt=”" width=”99″ height=”73″ />At SC12, Adaptive announced its Moab HPC Suite 7.2 release, which includes several productivity enhancements and introduces support for Intel Xeon Phi coprocessors. The workload management vendor also launched two new products as part of its Moab HPC Suite: Application Portal Edition and Remote Visualization Edition.

Adaptive Revs Moab, Debuts Remote Virtualization Edition

Nov 27, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpccloud/Adaptive_Computing_Moab_2012.jpg” alt=”" width=”92″ height=”67″ />At SC12, Adaptive announced its Moab HPC Suite 7.2 release, which includes several productivity enhancements and introduces support for Intel Xeon Phi coprocessors. The workload management vendor also launched two new products as part of its Moab HPC Suite: Application Portal Edition and Remote Visualization Edition.

Intel Adds Programming Support for Latest Silicon

Sep 6, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Parallel_Studio_Cluster_XE_2013_small.bmp” alt=”" width=”146″ height=”96″ />We’re only a little more than halfway through 2012, but Intel has already announced the 2013 versions Parallel Studio XE and Cluster Studio XE, two software suites that support x86-based parallel programming for high performance computing and beyond. Intel refreshes their software development offerings each year at about this time to sync up its tool support with the latest and greatest silicon and to add new features for developers.

HP, Intel Score Petaflop Supercomputer at DOE Lab

Sep 5, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/NREL_logo.gif” alt=”" width=”112″ height=”48″ />The US Department of Energy’s National Renewable Energy Laboratory (NREL) has ordered a $10 million HP supercomputer equipped with the latest Intel Xeon CPUs and Xeon Phi coprocessors. When completed in 2013, the system will deliver one petaflop of performance and will take up residence in one of the most energy-efficient datacenters in the world.

Intel Will Ship Knights Corner Chip in 2012

Jun 18, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”" width=”83″ height=”63″ />On Monday at the International Supercomputing Conference in Hamburg, Intel announced that Knights Corner, the company’s first manycore product, would be in production before the end of 2012. The company also released a few more details about the upcoming product line, including the creation of a new Xeon brand for the architecture, some performance updates on pre-production silicon, and Cray’s adoption of MIC as part of its future Cascade supercomputer.