The post Latest FPGAs Show Big Gains in Floating Point Performance appeared first on HPCwire.

]]>This is the fourth in a series of HPCwire articles comparing the theoretical floating point performance of Field Programmable Gate Arrays (FPGA) to microprocessors. As shown in the last article, the performance gap continues to expand between these two classes of devices. Comparing theoretical peaks for 64-bit floating point arithmetic, the current generation of Xilinx’s Virtex-7 FPGAs is about 4.2 times faster than a 16-core microprocessor. This is up from a factor of 2.9X as reported in 2010.

This article also includes some new empirical validation of the theoretical calculation by implementing a simple single-stream double-square function on two FPGAs using AutoESL, a C/C++ synthesis tool. That tool was able to implement a design within 2 percent of the theoretical predicted performance. The calculations were also supplemented by the hardware description language (HDL) implementation of a matrix multiplication (DGEMM) on one of the Virtex-7 FPGA devices.

**Background**

High performance computing applications have hit the practical limits of clock speeds for microprocessors. To increase the performance of a computing device, parallelism must be exploited so that more operations can be performed per clock cycle. For instance, multiple computing cores are being placed within the same microprocessor device. This keeps the programming model simple, since the same set of instructions can be spread across the multiple cores. The drawback is that a lot of circuitry is replicated that might not add performance. The Graphical processing unit (GPU) addresses this issue by providing more functional units sharing the same control logic.

FPGAs push this idea of parallelism to the limit via dynamic reconfiguration of the entire device, allowing the user to place only the functions and controls that are need for the calculation. The down side of this approach is that the complexity of the design must be handled by the programmer or hidden in FPGA design tools or pre-packaged libraries.

This design freedom on FPGAs also makes it difficult to gauge what the devices are capable of for 64-bit floating point performance. For this reason the first HPCwire article was written to describe one method to estimate the peak floating point performance of FPGAs. The concept was simple. Figure out all the ways floating point function units can be placed on a device and multiply it by the clock frequency from the data sheets. This method was further refined in a whitepaper published by Altera.

Since the FPGA is a blank sheet of transistors, some portion needs to be reserved for interfaces like memory controllers. In addition, FPGA design tools cannot make 100 percent use of the FPGA device, so some portion of the device area is needed to factor in this constraint. Lastly, not all the data paths between the floating point operators will be able to meet timing when packing a device close to its resource limits, so the data sheet clock frequency needs to be derated. Since different engineers might want to derate the FPGA devices in different ways for a predicted performance, the articles have been presenting both a “peak” floating point performance number that simply pack the FPGA with functions units and a derated “predicted” performance.

Soft floating point operators allow programmers to implement adders and multipliers in multiple ways and in any ratio needed. In contrast, the microprocessor has a fixed number of floating point function units, so the ratio of adders to multipliers is fixed. If a calculation only needs to perform additions, half the functional units (i.e. the multipliers) will become idle. This leads to an ambiguity regarding a device’s “peak” performance. Is it for an even ratio of adders to multipliers or for any ratio?

For this reason, the FPGA performance has been evaluated for both scenarios: an even ratio for direct comparison with microprocessors, and any ratio for a look at the optimal performance combination. The floating point operators supplied for these devices, come in 64-bit, 32-bit, and 24-bit versions. While it is very rare for a researcher in HPC to use 24-bit logic, these results show another dimension of the flexibility of FPGAs. If the calculations can make use of 24-bits, there is additional performance to be gained.

**Calculating Peak Performance**

The peak performance calculation of a Virtex-7 FPGA starts with collecting its available resources as reported from the data sheet, ds180. For example, the V7-2000T contains 1.2 million Look-up Tables (LUT), 2.4 million Flip-Flops (FF) and 2160 Digital Signal Processing (DSP) slices.

Next, the resource requirements for building functional units such as logic adders, full adders, logic multipliers, medium multipliers, full multipliers, and max multipliers are collected from the *LogiCORE IP Floating point Operator v6.0* data sheet, ds816. Some operators use more DSPs to run faster and use less logic.

With this data, it is just a matter of picking a configuration, adding up the LUTs, FFs, and DSPs needed, and seeing if they will fit on the device of interest. A program was written to systematically try every possible combination of the six types of floating point operators and multiplying them by the appropriate clock frequency, calculated gigaflops, then recording the best for each device. For the 64-bit floating point operators, the program was able to do a fully exhaustive search of every combination of operators. Because the 32-bit and especially the 24-bit operators are quite a bit smaller, many more will fit on a given device and hence the search space gets very large. For these precisions, a “step” function was used to regularly skip some configurations and do a semi-exhaustive search. This makes the performance predictions for the 32-bit and 24-bit performance more conservative.

Using this method, the best possible 64-bit floating point peak performance was calculated to be 670.99 gigaflops on the V7-2000T using 1469 logic adders and 196 max multipliers running at a 403 MHz clock. Further constraining the configuration to only look at adder/multipliers configurations with a one-to-one ratio drops the performance of the V7-2000T to 345.35 gigaflops. That configuration used 543 logic adders, 2 full multipliers, 237 medium multipliers and 304 logic multipliers running at a 318 MHz clock.

The floating point performance for the reference microprocessor is calculated by multiplying the number of floating point functions units on each core by the number of cores and by the clock frequency. For instance, the calculation for a 16-core device would be four 64-bit floating point ops per clock times 16 cores times 2.5 GHz, which comes to a theoretical peak of 160 gigaflops. Although clock frequency typically drops as the number of cores per microprocessor goes up, this article series has been using a normalized value of 2.5 GHz clock frequency for all microprocessor flavors for straightforward comparisons.

**Calculating** **Predicted Performance**

To calculate a more realistic “predicted” performance, some logic needs to be set aside for an interface and for routing the design. Xilinx recommended removing 20,000 LUTs and FFs for an interface and further reducing that by another 15 percent for routing to give a more realistic performance calculation. This is one of the reasons why the gap between the FPGAs and microprocessors has been growing. As FPGAs get bigger a smaller percentage of resources are need for the interface logic. Clock frequency is also reduced by 15 percent to simulate the longer data-paths in the design not meeting timing.

Applying those modifications, the predicted 64-bit performance of the highest peak V7-2000T performance drops 38 percent, from 670.99 to 484.02 gigaflops. It is interesting that the best predicted 64-bit configuration is still very similar to the peak performance configuration, using the same 196 max multipliers, but dropping the number of logic adders from 1469 to 1217.

The best one-to-one adder/multiplier ratio predicted 64-bit performance also drops 33 percent from 345.35 to 258.95 gigaflops. Again, the configuration looks very similar with the number of logic adders reduced due to the reduction of logic slices. This configuration is 479 logic adders, 3 full multipliers, 236 medium multipliers, and 240 logic multipliers running at a 270 MHz clock. For the microprocessor, its predicted performance is calculated by derating its peak performance by 85 percent.

While not practical for most HPC applications, the flexibility of having 24-bit floating point operators could yield over 1.6 teraflops on the V7-2000T.

One other aspect of the floating point performance that has yet to be explored fully is performing fixed point arithmetic within the FPGA and floating the results at the end of the calculations. At the lowest level, any floating point calculation involves a series of binary operations. Using floating point operators, the results are rounded after every calculation. This rounding takes up logic that could be used for more operators.

What if instead of rounding after each operation, the results was allowed to grow in bit-width and only floated at the very end? This would yield a more exact answer since there is no rounding and would use less logic.

**Validating Predicted Performance Using a Comparable Design Implemented in AutoESL**

To compare the validity of the calculated predicted performance, AutoESL was used to implement a simple design on two FPGA devices. AutoESL allows a programmer to write a high level description of the design in a standard programming language, which is then automatically synthesized into HDL. The HDL can be implemented into a design for an FPGA.

Using this tool, a double-square function was implemented on the X690T and X980T devices. The double-square function is a single-stream function that ties an arbitrary number of adders and multipliers together in one pipeline. An initial value is split, and passed as the two inputs to an adder. The output from the adder is then split and fed as the two inputs to a multiplier. The pipeline can be arbitrarily long and made up of an arbitrary number of adders and multipliers. With AutoESL, many combinations of the number and type of operators were tried to maximize performance for the target device.

This experiment created a double-square implementation for the X690T and X980T devices that were within about 2 percent of the predicted 64-bit floating point performance and validated the calculated predicted performance. For the X690T, AutoESL got timing closure on a 64-bit design using 390 full adders and 180 full multipliers running at 387 MHz for 220.59 gigaflops. The best predicted 64-bit performance was 224.03 gigaflops using 327 logic adders and 327 max multipliers running at a 342 MHz clock. For the X980T device, AutoESL achieved 282.5 gigaflops, where as the program calculated a 64-bit predicted performance of 289.45 gigaflops.

For these two data points the AutoESL designs shows that the predicted performance calculations can be obtained on simple algorithms and functions. The double-square function, though a simple algorithm was comparable to illustrate the validity of the upper limit of the predicted performance on a device.

**Comparing Predicted Performance against the Results of a Typical HPC Algorithm **

To demonstrate the performance limits of an FPGA when designing a complex design, a DGEMM algorithm was implemented on the X690T. DGEMM (“Double precision General Matrix Multiply”) is a standard routine from BLAS (“Basic Library of Algebra Subprograms”) and is commonly used for benchmarking HPC machines. The matrix multiply, a workhorse function for many scientific applications, happens to reap tremendous performance gains when accelerated on hardware within an HPC environment. Thus, the algorithm is apropos for this demonstration.

The FPGA fabric’s inherent parallelism allows the matrix multiply algorithm to be implemented using a systolic array of MACs (“Multiply-ACcumulate”) designed so that each MAC can calculate a continuous stream of dot products simultaneously. After analyzing the device specifications and going through a series of dry runs with smaller arrays, a 12×12 array clocked at 500 MHz could be attainable with reasonable effort. This architecture is shown in the figure below.

Several techniques had to be employed to maintain systolic operation (and hence, maximum performance) of the array throughout the algorithm’s execution, such as maximizing DDR3 efficiency, employing an innovative scheme for handling heavily-pipelined accumulators, using embedded RAM blocks as cache, and adopting a data re-use strategy while uploading matrix data from memory.

After carrying out an efficient floor planning strategy (a must for architecture of this complexity to meet 500 MHz), timing closure was met. The overall performance (number of MACs x 2 x frequency) measured out to 144 gigaflops, which works out to about 64 percent of the predicted limit of 224.03 gigaflops on the X690T.

There are opportunities for pushing this performance even higher. For instance, it is feasible that another row and column can be added and still achieve 500 MHz, resulting in a performance of 169 gigaflops, or 75 percent of the theoretical limit. Approaching it from a different angle, it’s possible to condense the arrays even further to create a 15×15 array, albeit at the sacrifice of clock frequency. In such a scenario, a 15×15 array clocked at 400 MHz would reach 180 gigaflops, or 80% of the predicted performance limit.

**Expanding the Niche of FPGAs in HPC**

The HPC computing landscape is moving towards heterogeneous computing using multiple threads internally on each computing device and tightly coupling thousands of devices together into large systems. Both manycore microprocessors and GPU fit well into this architecture.

FPGAs too can play well in this environment. They have the computing performance needed to compliment microprocessors, they have more flexibility to maximize the use of the given transistors, and they have the advantage of running at a lower clock frequency to lower their power requirements. Today FPGAs are used in some bioinformatics and financial applications. As researchers and companies improve the programmability of FPGAs with tools like AutoESL and pre-programmed libraries, the HPC community will find more uses for these accelerators.

**Related Articles**

**FPGA Floating Point Performance**

**Revaluating FPGAs for 64-bit Floating-Point Calculations**

**The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors**

The post Latest FPGAs Show Big Gains in Floating Point Performance appeared first on HPCwire.

]]>The post The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors appeared first on HPCwire.

]]>**Introduction**

Three years ago an article was published in HPCwire showing a method for comparing the peak performance of 64 bit floating-point calculations between FPGAs and a microprocessor. The article showed that the theoretical peak performance of the Virtex-4 LX200 was about 50 percent better than the then current dual-core processor. A follow-up article in HPCwire in 2008 refined these calculations, adding more detail to account for placement and routing issues in the FPGAs and using the latest release of the floating-point cores from Xilinx. These refined calculations compared three Virtex-5 FPGA devices against the then current quad-core microprocessor. That article showed that not only were the newer FPGAs faster than the quad-core processor, but that the gap in performance was getting larger. In 2009, six-core microprocessors were released and Xilinx released several new Virtex-6 FPGA devices. Recalculating the performance of all these devices shows that this gap in performance between the FPGAs and microprocessors continues to grow.

Recall that FPGAs are made up of an interconnecting fabric that are populated with Look Up Tables (LUTs), Flip-Flops (FFs), Configurable Logic Blocks (CLBs), Block RAM memory (BRAM), Digital Signal Processing (DSP) blocks, and other specialized features for performing I/O on these devices. On the Virtex-4 FPGAs, LUTs and FFs were arranged on the device with two LUTs and two FFs per logic slice and the DSPs were 18×18-bit multiply/accumulate units. The Virtex-4 BRAMs are18-bits wide. On the Virtex-5 FPGAs, LUTs and FFs are arranged in logic slices with four LUTs and four FFs per logic slice, DSPs are 25×18-bit multiply/accumulate and the BRAM is a mix of 18-bits and 36-bits wide. The Virtex-6 logic slices are now four LUTs and eight FFs making this the first time logic slices that are asymmetric with more FFs then LUTs. The DSP units remain 25×18-bit multiply/accumulate units. Finally, the BRAM is fundamentally 36-bits wide.

Beginning with the Virtex-4, Xilinx started making LX, SX, and FX versions of the FPGAs, with the LX maximizing the amount of logic slices and the SX maximizing the amount of DSP slices. This continues with the Virtex-5 and Virtex-6 devices. This article will use the Virtex-4 LX160 and LX200 [PDF], Virtex-5 LX330T, SX95T, and SX240T [PDF], and the Virtex-6 LX240T, LX550T, LX760, and SX475T [PDF] FPGA devices and a reference dual-core, quad-core, and six-core microprocessor.

As with the previous papers on this topic, theoretical peak performance will be calculated for all the devices. While peak performances can be seen as artificial, they are easy to understand and do show qualitative trends. More predicted performances will also be calculated to show a more quantitative comparison. The predicted performances actually gives an advantage to the FPGAs since the interface code size remains constant while the devices get bigger, giving proportionally more space for the user’s logic.

An interesting side bar about this project is the code used to calculate the peak performances on the FPGAs. The calculations look at all possible combination of the six function units (two types of adders and four types of multipliers) that will fit on the device. The maximum search space is then defined as the maximum number of adders of type one, times the maximum number of adders of type two, times the maximum number of multipliers of type one, times the maximum number of multipliers of type two, etc., for all six types of function units. For the Virtex-4, this search space ranged from 10^8 to 10^13 possible combinations which were reasonable for an exhaustive search. The Virtex-5 FPGAs are larger and the search space went from 10^10 to 10^17 possible combinations depending on the type of FPGA device being studied. Adding to the growing search space is the number of devices to test with two Virtex-4 devices, three Virtex-5 devices, and now four Virtex-6 devices. This required rethinking of the exhaustive search and reducing the search space by ignoring sub-domains that will not fit on the device. The Virtex-6 pushed the search space even higher, from 10^12 to 10^19 possible combinations. The code needed a complete rewrite to add a restart capability, parallelization, and a step function that allow for a near-exhaustive search.

The first task is to define a reference microprocessor. Both Intel and AMD have been making microprocessors for many years — both company’s microprocessors tend to leapfrog each other every year in performance — making it difficult to make a general statement about which processor is the fastest at a given point in time. AMD’s line of Opteron microprocessors: Santa Ana, Barcelona, and Istanbul are more or less equivalent to Intel’s Xeon microprocessor line: Woodcrest, Harpertown, and Nehalem. The peak performance used for the reference microprocessors in this article will be defined by a number of floating-point results per clock, times the number of cores, times the clock frequency. For the dual-core microprocessor, we used 2 flops/clock and for the quad-core and six-core, we used 4 flops/clock. This gives a peak performance for the dual-core of (2 flops/clock * 2 cores * 2.5 GHz) 10 Gflop/s, the quad-core of (4 flops/clock * 4 cores * 2.5 GHz) 40 Gflop/s, and the six-core of (4 flops/clock * 6 cores * 2.5 GHz) 60 Gflop/s for 64-bit floating-point results. The calculations are using the same clock frequency of 2.5 GHz for the microprocessors for easier comparisons. In reality, the clock frequency has been dropping as the core count goes up due to power constraints. For 32-bit and 24-bit results, these numbers can be doubled.

For FPGAs this peak can be represented as the available logic on the device, divided by the amount of logic needed to build a function unit, times the maximum clock frequency at which those function units will run. Calculating these peaks for FPGAs is more complicated since one can implement different ratios of add and multiply function units and use different ratios of logic and DSP resources. The microprocessors also only have one peak performance representing an equal ratio of additions and multiplications every clock cycle, whereas the FPGAs can have many peak performances.

Calculating the peak performance for FPGAs gets even more complicated since not only are there multiple devices, multiple ratios of additions and multiplications, but also because Xilinx supplies a set of floating-point cores to build function units, and these cores are improving over time. “Floating-point Operators v3.0″ (Xilinx document DS335) was first published in September of 2006. Version 4.0 of the same document was published in April 2008, and the latest version was published in June of 2009 [PDF]. As with compilers for microprocessors, each new floating-point core reduces its size and increases its performance. All the results shown here were performed with the latest floating-point operators, so the performance numbers of Virtex-4 and Virtex-5 may differ from results in previous articles.

The graphs above show the peak performance of the FPGAs as compared to the reference microprocessors. For the FPGA results, the peak performance was calculated for several devices of the same family and the best result plotted. The red line is the FPGA performance while forcing an even ratio of addition and multiplication function units on the device. These would give a fair comparison to the peak performance of the microprocessors since their best performance comes from having an equal number of additions to multiplications. The green line shows the peak performance of the FPGA devices by removing this restriction and finding the optimal mix of function units for the best possible peak performance. Clearly from a peak performance point of view the FPGAs are outpacing microprocessors. This can be explained by thinking about what happens inside the devices as they grow. For the microprocessor the whole computing core is replicated. While this adds another set of function units, it also adds all the overhead needed to manage those functions, whether they are used in the calculation or not. On the FPGA side, adding more space on the device allows the programmer to add more function units that are used in the calculation. This makes the percentage of the device doing useful calculations higher then on the microprocessor.

**Calculating Predicted Performance**

The same calculations were performed to calculate a more predicted performance for both the microprocessors and the FPGAs. Looking at results from the HPL benchmark, microprocessors typically get 80 percent to 90 percent for the peak performance running this benchmark. While this benchmark is somewhat artificial compared to what an application might get, it is useful in showing the performance of a calculation actually running on the device. For the results presented here, 85 percent of the peak performance was used as the predicted performance for the microprocessors.

While an actual calculation has not yet been synthesized and implemented on the FPGAs, working with Xilinx engineers, the predicted performance has been calculated by using a reduced clock frequency of 15 percent and a reduced amount of available logic, by first removing 20,000 LUTs and 20,000 FFs for an I/O interface and an additional 15 percent reduction for placement and routing.

The graphs to the left show the same trends. The FPGAs are growing in performance faster than microprocessors. This trend gets even bigger when non-standard floating-point operations are considered. Note how the 24-bit floating-point performance continues to grow over 32-bit floating-point performance on the FPGAs. This is because an FPGA does not have a fixed word size and can reconfigure the logic into exactly what it needs for the calculation. Microprocessors on the other hand can only do 64-bit or 32-bit floating-point operations, and these graphs are simply repeating the 32-bit results for the 24-bit calculations. If you extend this to applications that work on the bit level, like compression/decompression, searches, and encryption/decryption, FPGAs have shown two orders of magnitude better performance.

While FPGA performance is growing, the ease to program them has not. Programming an FPGA still requires a highly skilled programmer/engineer to develop the code for the device. However, once developed standard C/Fortran applications can call them as specialized subroutines. This difficulty in code development is due to the programmability of the device. The programmer needs to create the function units needed for the calculation and also all the caching and memory operations. While this allows for a calculation to take full advantage of every bit of circuitry available on the device, it makes them much harder to program.

It should also be noted that these graphs are considering the devices themselves and are not taking into account the amount of time needed to export data, if needed, to a separate device. Typically an FPGA is used as an accelerator attached to a microprocessor, thus any speedup achieved by the attached accelerator needs to be reduced by the amount of time needed to move the data from the microprocessor to/from the accelerator or the calculations and communications needs to be overlapped. The graphs also do not consider the effects of using local memory during the calculations.

To better understand the raw computing performance of the FPGA, consider the latest SX475T with 74,400 logic slices and four LUTs per slice, giving it a total of 297,000 LUTs. Recall that a LUT is a “Look Up Table” with two outputs per LUT. A logic slice also has many Flip-Flops, but those are used to split a signal for routing and do not contribute to an operation. This gives the device, running at a conservative speed of 250 MHz, 2.32 trillion 64-bit op/s (297,600 LUTs * 2 bit operators per LUT * 250 MHz * 1/64). A six-core microprocessor running at 2.5 GHz would have 60 billion 64-bit op/s (6 cores * 4 ops per clock * 2500 MHz). This gives the FPGA 38.7 times more raw computing power.

Clearly, microprocessors are hitting their limit in serial processing and programmers are now forced to make their codes more parallel on multi-core microprocessors. Other options programmers have are to look at accelerators such as FPGAs, GPUs, or other specialized hardware. Any of these accelerators need a new development environment to write the code. For the FPGA, the development tools continue to improve as well as the IP cores used as the basic building blocks of these new accelerator algorithms. Most of all, FPGAs typically run at about a 10x slower clock rate which makes them use about a third to a quarter of the power as a typical microprocessor. As the number of devices needed to reach a petaflop grows, having these low power accelerators helps HPC systems fit within a reasonable power envelope.

Xilinx has now released the Virtex-7 [PDF] and new microprocessors are available, so it is time to start another set of comparison calculations.

The post The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors appeared first on HPCwire.

]]>The post Convey Debuts Second-Generation Hybrid-Core Platform appeared first on HPCwire.

]]>Convey’s first HC-1 design, unveiled at SC08, began production shipment in 2009. Although still in startup mode, Convey seems to be on sound financial footing. They collected their second round of funding last summer, bringing their total to $40 million. Since then the company has increased its head count from 25 to 55.

According to company president and CEO Bruce Toal, they now have roughly 30 customer deployments, ranging from single units up to 8-node clusters. The majority of the systems have been installed for bioinformatics, government and research applications, with financial services, energy and logic simulation also represented.

Because of the platform’s malleability, it can serve virtually any HPC application domain. The basic concept is to offer a standard x86 server platform, but accelerated by FPGAs in the guise of a co-processor. For a specific application domain (or even just a single application), the FPGAs are programmed to extend the x86 ISA with custom instructions intended to accelerate the target software. These instructions are then generated by the Convey tools during source compilation. It’s a nifty little design, and worlds away from the more typical FPGAs-as-an-afterthought HPC approach that has been used in the past.

The CPU and FPGAs are glued together via the shared memory subsystem, which blends the x86 memory to the customized high performance memory on the co-processor side. This allows both of them to work within the same cache-coherent shared memory space. The approach is quite different from a conventional HPC accelerator, which typically treats the FPGA, GPGPU, or whatever as an I/O device, hanging off a PCI-Express slot. In Convey’s model, the FPGAs are virtualized and act as a true co-processor. “It enables you to build a completely integrated compiled environment, which we believe is a fundamental element for hybrid computing,” explains Toal.

The HC-1^{ex} is the higher end version of the HC-1 but, according to Toal, is not a replacement for the original. In the second-generation product, the company has upgraded the dual-core Xeon to a quad-core part, and increased CPU memory capacity from 64 GB to 128 GB. More importantly, though, the HC-1^{ex }has moved up to the latest generation Xilinx Virtex-6 FPGA (the LX760) from the Virtex-5 part (the LX330) in the original HC-1. The newer 40nm FPGA offers more that three times the gates of its predecessor.

Assuming the application can take advantage of those additional gates, that translates to higher absolute performance, better price-performance and increased performance per watt. For example, using a Smith-Waterman search (a nucleotide sequencing algorithm that scales extremely well on FPGAs), the HC-1^{ex }performed 401 times faster than a single-core Intel CPU. That’s more than twice the performance of the HC-1. The general idea is to replace multiple racks of conventional servers with a single rack of Convey gear, so as to reduce floor space requirements, power usage and overall total cost of ownership (TCO).

The first HC-1^{ex }was deployed at Georgia Tech in September. Rich Vuduc, assistant professor School of Computational Science and Engineering, is leading a research team to apply heterogeneous computing systems to data analysis and data mining applications. With the HC-1^{ex }, Vuduc is developing a custom FPGA personality for his particular data analytics domain. The work is being partly funded under a DARPA contract, so one could surmise the work could end up in some interesting defense- or security-related applications .

Beyond the HC-1^{ex }unveiling, Convey is also announcing some new partnerships this week. These include Panasas, AutoESL, Impulse, Jacquard Computing, and Voci Technologies. The Panasas collaboration will bring the company’s storage client software into the Convey OS and cluster framework software. The next three, AutoESL, Impulse and Jacquard, are providing higher level FPGA programming tools to help develop co-processor personalities.

The last-mentioned partner, Voci, is actually OEMing the Convey gear in the form of a speech recognition appliance. Called V-Blaze, the appliance can process a hundred phone conversations in real time and convert the conversations to text. The idea here is to be to transform phone conversations into text, which can then be keyword searched for further analysis. One application would be call center monitoring. Purportedly, the V-Blaze appliance delivers much better resolution and lower error rates than commercial voice recognition products. That’s 100x better than a single CPU could accomplish and perhaps 10x better than a GPGPU implementation.

The Voci collaboration is a good example of how Convey can expand its market other than through direct end user sales. But Toal does expect to see sizable growth in such sales over the next year, thanks to a larger distribution channel and the additional technology partnerships, not to mention the new HC-1^{ex }offering. Fighting the GPGPU juggernaut won’t be easy, but the true believers at Convey seem determined to do so.

The post Convey Debuts Second-Generation Hybrid-Core Platform appeared first on HPCwire.

]]>The post The Week in Review appeared first on HPCwire.

]]>James River Technical Becomes Reseller for Bright Computing

Xilinx Stacked Silicon Interconnect Extends FPGA Technology

Oracle Makes Strategic Investment in Mellanox Technologies

IBM Analytics Software Used to Uncover Stroke Complications

Software Speeds Up the Processing of Gigapixel Images

Cray Lands $60 Million Contract from University of Stuttgart

Voltaire Fabric Collective Accelerator Available for Platform MPI

CAPS Adds HMPP Support for Windows HPC Server, Visual Studio

T-Platforms, U of Heidelberg to Develop New HPC Interconnect

Lawrence Livermore Expands Use of Rogue Wave Acumem Software

Teradata’s Updated Platform Family Sports Intel Processors, SSD Technology

Tsinghua University Deploys NAG Numeric Library

The Beagle Has Landed in Chicago

Berkeley Lab in Search for New Director of Computational Research Division

**Chinese Introduce World’s Fastest Supercomputer**

NVIDIA got the chance to beat its GPU computing drum today mere weeks before the SC10 conference takes place in New Orleans. China’s premier supercomputer, Tianhe-1A, powered by NVIDIA’s graphics chips (7,168 of them, in fact), made its official debut today at HPC 2010 China. The machine has set a new performance record of 2.507 petaflops, as calculated by the LINPACK benchmark. By that measure, Tianhe-1A is the fastest system in the world today, likely destined to grab the coveted number one spot on the next TOP500 list to be announced at SC.

This degree of speed was made possible by GPUs, specifically NVIDIA Fermi Tesla GPUs. The game-changing nature of these graphics processors is illustrated by the fact that GPUs now power two of the top three fastest computers in the world today; China’s “Dawning” system is currently sitting in the number two spot on the TOP500.

From the release:

Tianhe-1A epitomizes modern heterogeneous computing by coupling massively parallel GPUs with multicore CPUs, enabling significant achievements in performance, size and power. The system uses 7,168 NVIDIA Tesla M2050 GPUs and 14,336 CPUs; it would require more than 50,000 CPUs and twice as much floor space to deliver the same performance using CPUs alone.

More importantly, a 2.507 petaflop system built entirely with CPUs would consume more than 12 megawatts. Thanks to the use of GPUs in a heterogeneous computing environment, Tianhe-1A consumes only 4.04 megawatts, making it 3 times more power efficient — the difference in power consumption is enough to provide electricity to over 5000 homes for a year.

For deeper insight and a comparison of China’s preeminent system with the United State’s own fastest, Jaguar, be sure to check out HPCwire Editor Michael Feldman’s blog post.

According to Feldman, if the Chinese still hold their lead come next month’s TOP500 installment, this will be the first time that a non-US machine took the number one spot in six years, before which Japan’s Earth Simulator reigned from 2002 to 2004. Feldman also astutely points out that the US, Germany, and the UK currently have no GPU-equipped systems on the TOP500.

**Cray’s Cascade System to Debut at University of Stuttgart**

Cray marks another XE6 win this week. Cray and the University of Stuttgart announced Tuesday that Cray would provide a supercomputing system for the university’s High Performance Computing Center Stuttgart (HLRS). The contract has two phases, the delivery of a Cray XE6 supercomputer in 2011 and the future delivery of Cray’s next-generation supercomputer code-named “Cascade” due out the second half of 2013. Consisting of products and services, the deal is valued at more than $60 million (45 million euros) and follow-up expenses are estimated at $40 million (30 million euros) for maintenance and energy.

The supercomputer will strengthen the computing prowess of the entire European community. From Cray’s release:

The new Cray system at HLRS will serve as a supercomputing resource for researchers, scientists and engineers throughout Europe. HLRS is one of the leading centers in the European PRACE initiative and is currently the only large European high performance computing (HPC) center to work directly with industrial partners in automotive and aerospace engineering. HLRS is also a key partner of the Gauss Centre for Supercomputing (GCS), which is an alliance of the three major supercomputing centers in Germany that collectively provide one of the largest and most powerful supercomputer infrastructures in the world.

The announcment is short on system specs, such as core counts and FLOPS, but the nature of the Cascade system and a statement from the director of HLRS point in the direction of petaflops:

“HLRS and Cray have enjoyed a long history in ensuring our researchers and scientists are equipped with innovative supercomputing systems that are built with leading-edge supercomputing technology,” said Prof. Dr. Michael Resch, director of HLRS. “Cray is just the right partner as we enter the era of petaflops computing. Together with Cray’s outstanding supercomputing technology, our center will be able to carry through the new initiative for engineering and industrial simulation. This is especially important as we work at the forefront of electric mobility and sustainable energy supply.”

The highly-anticipated Cascade supercomputer will feature Cray’s Linux Environment, its HPC-optimized programming environment, and a next-generation interconnect chipset code-named “Aries,” which is a follow-on to Gemini. Additionally, Cascade will be Cray’s first capability supercomputer based on Intel x86 processors. Cray explains that Cascade was made possible in part by the Defense Advanced Research Projects Agency’s (DARPA) High Productivity Computing Systems program. Cascade’s novel design will likely set the stage for future exascale architectures.

The post The Week in Review appeared first on HPCwire.

]]>The post Intel Linked with HPC Boost Buy appeared first on HPCwire.

]]>The post Intel Linked with HPC Boost Buy appeared first on HPCwire.

]]>The post Analyst: Intel May Acquire FPGA Vendor appeared first on HPCwire.

]]>The post Analyst: Intel May Acquire FPGA Vendor appeared first on HPCwire.

]]>