HPCwire: Heterogeneous Processing: Trite or Trend?

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June 24, 2009

Heterogeneous Processing: Trite or Trend?

by Dr. Vincent Natoli, President and Founder, Stone Ridge Technology

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Heterogeneous processing or co-processing on chips other than the CPU is the most recent trend in HPC. To some extent there has always been a small fringe element pursuing this direction, but as recently as a few years ago, a colleague claiming to be coding a GPU for physics or chemistry calculations would have been politely avoided. Programming FPGAs in strange hardware languages was even more far-fetched.

In the past few years, however, there has been a rich diversity of efforts and support from major HPC vendors. This year brings at least two conferences focused on heterogeneous computing: The Symposium on Application Accelerators in HPC (SAAHPC09, U. Illinois-Urbana, July 28-30) and the CECAM workshop "Algorithmic Re-Engineering for Modern Non-Conventional Processing Units" (Lugano, Sept. 30-Oct. 2). Several other meetings are dedicated to one type or another of specific co-processing approaches.

The most prominent examples of heterogeneous elements and efforts in HPC include the rapidly growing GPU computing community supported by NVIDIA and AMD/ATI and reconfigurable computing on field programmable gate arrays (FPGAs). C-based APIs, such as CUDA put out by NVIDIA, have opened up GPU computing to a much wider audience. Other examples include the IBM Cell chip and ASICs, such as those available from ClearSpeed, as well as soon to be released chips with built-in heterogeneous elements, such as Intel's Larabee and AMD's Fusion.

As more HPC practitioners are adopting these platforms today, many organizations are now taking a second look and evaluating them for their needs. Companies, university departments and government agencies want to know if heterogeneous processing is another fleeting trend or a real, sustainable technology transition driven by long-developing forces. The questions organizations are asking are: Will heterogeneous processing be an integral part of future HPC? Is it here to stay? To attempt an answer it's useful to consider the recent past of HPC that has been characterized by a move to computing on large clusters of commodity chips.

Recent Trends in HPC

The share of the TOP500 machines using x86 programmable machines progressed from negligible in 1999 to roughly 90 percent in 2009, the balance comprised mainly of IBM Power. The numbers for cluster architectures versus MPP and others show the same development. The progression toward HPC computing on large clusters of commodity computing has had many positive impacts, providing great price/performance ratios and a large pool of qualified programmers by pushing affordable and scalable technology down to the department level. While clock speed increased reliably HPC practitioners were willing to turn a blind eye to the deficiencies of commodity solutions; happy to type make on their new platforms and see a doubling of performance every two years. The party ended in 2004, however, when clock speeds began to stall and the problems of HPC commodity computing became more salient, especially the memory wall (further reading here and here) and the divergence problem.

The story of power dissipation and the saturation of CPU clock speed is by now well known in HPC. With more silicon area available and the inability to jack up clock speed further, CPU vendors did what any clever vendor would do -- provide more of their key product on die. At Intel it was called "the right hand turn" and it began to show effect in the market in 2004. Before 2004 data from the TOP500 list shows that FLOP performance improved at a healthy factor of 1.8 per year with 1.4 from improved clock and 1.3 from simply having a bigger machine. Plotting machine size against time shows a clear inflection point around 2004 after which machines have mainly improved performance and kept on trend by using more and more cores for processing. The multicore transition started with two cores, is currently at four and six cores, and will soon move to eight cores and higher.

Problems with Commodity HPC

The truth though is that many -- in fact, most -- HPC codes don't scale well past 16 processors at least in their current form. In a world where performance can only be improved by use of more cores this is not great news. In short, commodity trends have led to great capacity solutions but not capability systems. Seymour Cray stated it succinctly as "If you were plowing a field, which would you rather use? Two strong oxen or 1024 chickens?" Clearly one of the seminal influences on HPC and supercomputing preferred oxen to chickens, but the HPC menu appears to favor poultry at the moment.

The recent percolation in the market of heterogeneous or co-processing solutions may be viewed as a response to this capacity/capability gap and the opportunity to use the new silicon area offered by Moore's law for something other than CPU cores. Once programmers understand multi-level parallelism is required or they reach the scaling limits of their problem, adopting a novel platform to achieve more performance does not seem unreasonable.

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