San Jose, CA — ARC Cores Ltd, announced the integration of its 32-bit user-configurable microprocessor core as the foundation for Hyperchip’s petabit (one thousand trillion bits/second) router design.
For the first time, the processing power necessary to accommodate high-end terabit- to petabit-scale routing is attainable for next generation networking and communications applications. Utilizing the extremely small size of the ARC processor core, Hyperchip was able to cluster multiple cores into a single massively parallel chip for packet processing. The ingenious register interface of the ARC architecture allows 32 cores to be clustered into a single chip and integrated with routing accelerators without the bus bottlenecks that other licensable processors would create. In addition, the fully configurable ARC processor core gave Hyperchip the flexibility needed in designing-in only the features necessary for their application, further reducing the chip real estate needed for the 32 cores.
After evaluating a number of processor solutions, Hyperchip chose the ARC processor because of its highly configurable nature and ease of design integration. Its availability as a soft (synthesizable) core gave Hyperchip’s designers full control over the processor’s functionality, without the performance hit typical of other soft cores.
“We looked at everything out there and came up with two alternatives: roll our own or use the ARC processor. ARC provided everything we would have put in a core had we designed it in-house, and better optimized” said Richard Norman, President & CTO of Hyperchip. “Our design would not have been as powerful as the ARC core, nor would we have been able to cluster as many cores on a single chip. Because of the inherently flexible nature of the ARC core, we were able to modify the ARC source to provide it direct access to and control of our propriety hardware functions.” Hyperchip’s architecture, which utilizes massively parallel processing to achieve extreme performance, scales to offer petabit-routing in compact air-cooled units.
“The ARC is a fairly simple, but extraordinarily flexible, processor design,” said Jim Turley, ARC’s vice president of marketing. “It takes visionaries like the folks at Hyperchip to realize its full potential. We provided Hyperchip with the means to design a network processor to fit their needs and they ran with it. When you combine them the end results can be impressive.”
Hyperchip is reportedly the first company to develop routing systems that scale to petabit performance. A Hyperchip Matrix provides this scalability to server, storage, local and wide area networks at one tenth of the cost of today’s gigabit and terabit architectures. Hyperchip’s products are suited for large e-commerce sites, network service providers, and telecommunications points-of-presence.
For more information visit http://www.arccores.com