San Jose, CALIF. — PACT Corporation, a fabless semiconductor and intellectual property company based in Munich, unveiled the eXtreme Processor Platform (XPP) for advanced, processing-intensive high-bandwidth applications. Based on an innovative architecture, the eXtreme Processor enables designers to easily use massively parallel processing to reach unprecedented performance and bandwidth levels.
The first eXtreme Processor, the XPU128, has demonstrated performance that is up to 50 times greater than conventional sequential processors and 20 times higher than digital signal processors (DSPs), which are basically sequential processors fine-tuned for signal processing. The first XPP device achieves sustainable peak performance in excess of 50 Giga Operations per second (GigaOps), making it the world’s most powerful 32-bit processor. “The XPP can be an enabler for a number of new digital signal processing (DSP) applications that were not practical until now. For example, it will likely be a serious market contender for the next generation of base station smart antennas, an application that many feel will explode with the emergence of third-generation cellular,” said Will Strauss, president of Forward Concepts, a market research firm in Tempe, Arizona. “But PACT’s XPP is not limited to the DSP market, since it is a new class of processing engine with unrivaled computing performance that is ideally suited for many other computing-intensive applications, as well.”
The scalable architecture of the XPP enables broad applicability to a wide range of applications. For applications where cost or power consumption is paramount, PACT provides intellectual property (IP) cores that are easily integrated into standard cell and system-on-a-chip devices. XPP IP cores are ideal for the next generation of multifunctional high bandwidth devices, including Internet appliances, PDAs, and mobile telephones for which extreme processing power enables higher levels of functionality and enhanced user interfaces.
For applications that require maximum processing power, PACT supplies eXtreme Processing Unit (XPU) devices. XPP components are targeted at midrange applications such as 3G cellular base stations and voice over IP (VoIP), where they help deliver higher call quality and the ability to handle a much larger number of calls than previously thought to be possible. In addition, cascaded arrays of XPU devices supply the processing performance and bandwidth demanded for extreme applications such as the next generation of supercomputers.
Conventional processors, such as RISC or CISC, use a sequential model to process data. These processors store operands in registers and fetch instructions from memory; then move the operands into the processing unit where the processor performs calculations; and then send results into another register. This model is efficient for sequential applications where different operations are applied to each data word.
However, the sequential model is very inefficient for high-speed broadband applications such as mobile communications, which apply the same algorithm to each data word in a multi-channel data stream. The processor overhead – the process of moving each word into a central processing unit, fetching an instruction, and moving the word to a result register – creates a huge bottleneck that severely limits system performance and bandwidth.
To break the bottleneck, XPP’s reconfigurable parallel data flow processor sends high-speed data streams through an array of processing elements at full speed. The processor performs calculations during each clock cycle. The results then flow to the next processing element. This process continues until all calculations specified in the algorithm have been completed and all of the processed data has flowed out of the XPP.
In addition to raw broadband processing power, the XPP platform offers design methodologies that enable designers to easily and efficiently use high bandwidth parallel processing. A major breakthrough implemented in the XPP platform is the Wave Reconfiguration technology that transparently configures processing elements as data flows through the array.
PACT’s Wave Reconfiguration model is ideal for emerging multi-service broadband networks that use packetized data to support voice, audio and video. For example, if the first packet flowing through the network contains voice data, the XPP is configured for the voice-processing algorithm. The voice packet streams through the array and is processed at full speed. As the next packet enters the array, a token attached to the front of the packet identifies it as a video packet. This token rides just in front of the wave of video data and triggers reconfiguration of each processing element one clock cycle before the data arrives. The result is a wave of reconfiguration that programs the processing elements with the video algorithm at precisely the right time as data flows through the array.
Wave Reconfiguration allows programmers to easily make tradeoffs between performance and density and to minimize power consumption. For example, conditional branch execution can be implemented by programming each branch into the array for maximum speed or using Wave Reconfiguration to configure processing elements as branch evaluations are completed.
For the control portion of applications, Wave Reconfiguration enables the XPP to instantly configure resources to efficiently process sequential operations eliminating the need for a separate sequential processor. For power sensitive applications, Wave Reconfiguration turns off clocks for unconfigured elements and processing elements dynamically power themselves down when data streams are not active.
The XPP contains many additional features that free the designer from chip-level details and make it simple to use. Automatic DataFlow Synchronization ensures that all data inputs are valid before nodes are calculated eliminating the need for lengthy timing verification and optimization. A configurable internal event network enables control of program flow using flags like conventional processors.
The XPP uses a flow-graph style design methodology familiar to microprocessor and DSP design engineers. PACT’s Native Mapping Language (NML) allows users to easily express arithmetic constructs targeted to XPP processing elements. Tools that enable even higher levels of abstraction are in development including C compilers and a flow-graph style language called LELA, developed for PACT by Professor Niklaus Wirth, the inventor of PASCAL.
PACT’s first device, the XPU128, contains an array of 128 parallel processing elements implemented in advanced reprogrammable technology. Each element performs high-speed, 32-bit signed and unsigned operations that execute in a single clock cycle.
The XPU128’s I/O are organized into eight modules, each containing dual 32-bit high-bandwidth channels. The device contains 32 independent 1K-byte embedded SRAMs for high-speed access to source data, destination data, and look-up table contents. These internal SRAMs can be configured as FIFO buffers to support burst-oriented applications. Multiple interfaces to external RAMs provide high distributed memory bandwidth.
A point-to-point internal terabit dataflow network connects XPU resources without the bottlenecks of a bus-oriented architecture. This network makes one-to-many and many-to-one connections between neighboring or distant XPU resources anywhere on the device. A separate second configurable event network transports control flow information. And a third network provides transparent and background reconfiguration capabilities for not only the processing elements, but also for the array’s interconnect. The XPU128 offers high levels of processing power and bandwidth:
— 51.2 GigaOps (32-bit)
— 12.8 GigaMACs (32-bit)
— 3.2 Gigabyte/s external memory bandwidth
— 12.8 Gigabyte/s internal memory bandwidth
— 6.4 Gigabyte/s sustained I/O bandwidth
— 0.4 Terabyte/s internal data bandwidth
The XPU’s modular and truly scalable architecture enables its performance to scale much more efficiently than conventional processors. PACT’s product roadmaps show devices with over 400 GigaOps per second in 2002 and over the PetaOps (1,000,000 GigaOps) level within the next decade.
“Vendors of classical processors rely primarily on higher clock frequencies to achieve incremental performance gains,” said Martin Vorbach, PACT’s co-founder, chief technology officer and the inventor of the XPP. “XPP achieves a second dimension of performance gains by scaling not only with clock frequency, but also with the number of processing elements. Utilizing advanced process technology, we can soon put over 1000 processing elements on a single chip.”
XPP intellectual property cores and PACT’s development system with NML are available for license today. The LELA programming language will be available in Q1 2001. XPU128 devices will be available in production quantities in Q1 2001.
PACT is a fabless semiconductor and intellectual property vendor developing extreme performance processor platforms. The company’s patented breakthrough technology results in a new class of processor, which delivers extreme bandwidth and processing performance for a wide range of applications including portable communication devices, next generation base stations and supercomputers. The company was founded by Marcel Kreutler and Martin Vorbach in Germany in 1996. PACT’s eXtreme Processor Platform, XPP is covered by over 20 international patents in both processor architecture and reconfigurability. PACT currently has offices in Munich, San Jose, New York, Atlanta and Tokyo. The company can be reached at http://www.pactcorp.com .