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Dallas, Texas — Synopsys, Inc. has announced that Cray Inc. has
successfully taped out an eight million-gate, 450 MHz, vector processor ASIC using Synopsys’ Physical Compiler. The design was implemented using a copper-based 0.12-micron process technology. The chip, code named Processor Vector Cache (PVC), is being used in the new Cray SV1e(TM) scalable-vector supercomputer, which was announced at the IEEE Supercomputing 2000 conference.
Cray incorporated Physical Compiler into its ASIC flow as a CAD tool enhancement to achieve aggressive SV1e project objectives. Cray was able to use Physical Compiler with less than a week of startup effort, by leveraging its current Design Compiler infrastructure. With Physical Compiler central to their timing-closure flow, Cray achieved their very aggressive circuit performance goals while saving significant design time.
“As a builder of the world’s most capable supercomputers, Cray is constantly pushing the limits of circuit design,” said Gary Shorrel, Cray SV1e engineering project manager. “The PVC chip was difficult even by Cray’s standards, and achieving timing closure was a significant challenge. Using Physical Compiler’s capabilities enabled us to achieve our aggressive target frequencies. Physical Compiler fit right into our ASIC flow and we were able to get up to speed in under a week. Physical Compiler reduced the overall design cycle and eliminated the painful iterations by enabling placement handoff to the ASIC vendor.”
“Cray’s ASIC designs challenge even the most sophisticated vendor flows in achieving timing closure,” said Sanjiv Kaul, senior vice president and general manager of the Physical Synthesis business unit at Synopsys. “In addition to helping our customers achieve their target performance goals in the shortest time, Physical Compiler’s placement handoff is adding predictability into the flow, allowing them to meet their time to market requirements.”
Synopsys’ Physical Synthesis Solution
Pioneered by Synopsys, Physical Synthesis helps designers address the implementation challenges of next-generation system-on-chip designs. Physical Synthesis brings key physical design considerations forward in the design flow, allowing RTL designers to rapidly achieve high quality of results. The overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement, and FlexRoute top-level router. Synopsys’ Physical Synthesis leverages industry-standard tools such as Design Compiler(TM), Module Compiler(TM) and PrimeTime(R) and its proven interfaces to third-party solutions allow it to easily plug into an existing design flow.
About Cray Inc.
Cray Inc. is the global market leader in high-end supercomputers. Cray Inc. is dedicated to helping customers solve the most demanding, most crucial computing problems on the planet — designing the cars and trucks we drive, creating new materials and life-saving drugs, predicting severe weather and climate change, analyzing complex data structures, safeguarding national security, and a host of other applications that benefit humanity, by advancing the frontiers of science and engineering. Visit Cray Inc. at http://www.cray.com/company/about.html
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.