DARESBURY HOSTS MACHINE EVALUATION WORKSHOP

December 1, 2000

by Christopher Lazou

San Diego, CALIF. — Some 130 people from computer vendors, computer service providers and researchers in scientific fields, a few from industry, but mostly from UK universities, attended the 11th machine evaluation workshop at EPSRC Daresbury Laboratories, UK. Of great interest were the Beowulf solutions, where clusters can be cobbled from favoured commodity Chips and Interconnect Network to fit one’s pocket, and hopefully computing needs.

This established workshop provided a plethora of distributed memory benchmark results on the latest products from vendors using their latest chips. The benchmark suite used consists of many computational chemistry kernel codes, molecular dynamics, Quantum Monte Carlo, Jacobi Solver, STREAM – measured sustainable memory bandwidth in HPC (TRIAD), the Ab Initio molecular electronic structure, the DL_POLY, parallel molecular dynamics benchmark, developed by Daresbury. The suite also includes SPECfp95 and other well known benchmarks. Martin Guest and other Daresbury staff described their benchmark findings, comparing the cost/performance of many available systems.

The rest consisted of vendor presentations, user experience in building their own Beowulf clusters and presentations from a small number of companies specialising in providing Beowulf solutions from commodity components on demand. Instead of buying pre-packaged products from traditional vendors, a cluster can be cobbled from favoured Chips and Interconnect Network to fit one’s pocket and hopefully satisfy computational needs.

Vendor presentations included the new IBM RS/6000 Power 4 chip and its promise of a theoretical peak performance of 140 Gflop/s on a 32-way board; the SGI Origin3000 based on MIPs technology and their road map showing developments until year 2005; the Compaq Alpha EV7, the Sun Microsystems Ultra SPARC and so on. I would not bore you here with details as I am sure they have been reported in articles on SC2000 in Dallas only recently.

At this workshop only NEC was representing the heavy weights of parallel vector processor supercomputing. Toine Becker, gave a brief history of the CMOS version of the SX-4 and SX-5 systems. He re-iterated NEC’s commitment to PVP systems with improved speeds, the SX-6 in year 2002 and an SX-7 in year 2003+. He also briefly described the Earth Simulator with its 40 Tflop/s peak performance.

In Europe, NEC is concentrating in capability computing whilst in Japan is strong in capacity, the server commercial market. It is involved in the AzusA/AsamA IA-64 project, to place 4 CPUs in a box. Each CPU runs at 800 MHz, 1.6 Gflop/s. AzusA is a 16 way IA-64, the AsamA is a McKinley 32 way which is planned for year 2002. A 64 to 512 way (32 way xN) node is expected by year 2005. Note that in the McKinley and Madison chips, vectors are introduced, which will bring costs down dramatically for HPC systems.

What has transpired is that almost all vendors though continuing their own product line, are also actively planning to incorporate the Intel IA-64 Chip, and its successors McKinley and Madison, in their near future server products. Indeed, the speaker from HP, having described their current PA-RISC line, proceeded to say that HP anchored their business, gambled the whole company, on the success of the IA-64 architecture.

The exception is Sun Microsystems which is sticking to its RISC technology. HPC vendors are also busy open sourcing their compilers and other software tools for Redhat, Susa, and Turbo LINUX, which they intend to use on the Intel IA-64.

There is now general agreement that what ever else, “the ASCI experience taught us, memory bandwidth and latency are the key components which will deliver performance. Without doubt a fast memory sub-system is critical for high sustained performance; and in addition, with the advent of multi-level cache Chips, compiler technology is becoming very important for extracting performance”. At present processor speed is increasing faster than memory and compiler technology. This means that sustained performance would be but a shadow of peak. What vendors are promising is 100 Tflop/s peak by year 2004-5, at a price of $2 per Mflop/s. Sun Microsystems goes even further claiming they would offer HPC for $500/Gflop/s with their 128 CPUs “Javawulf” cluster by year 2003. They plan to offer Java based HPC which should allow applications to run on anyone’s hardware. SUN claims they are undercutting an Intel environment by at least 20%.

Copyright: Christopher Lazou, HiPerCom Consultants, Ltd., UK. Email: [email protected]

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