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San Diego, CALIF. — With a research paper and images from an electron microscope, Michael Kanellos reports that Intel plans to show that Moore’s Law will hold for another decade.

The Santa Clara, Calif.-based chip giant will release a paper at the IEEE International Electron Devices conference in San Francisco showing that the company can produce transistors with elements as narrow as eight angstroms, or three atoms, far smaller than today’s chips.

The achievement is significant in that it shows there are no known physical barriers to slow the pace of chip performance growth for the next five to 10 years, said Gerald Marcyk, director of Intel’s Components Research Lab.

Moore’s Law, formulated by Intel co-founder Gordon Moore, states that the number of transistors a chip can hold will double every 18 to 24 months, as transistor size shrinks. More transistors, which switch off and on to represent binary data, lead to a corresponding leap in performance.

Real time translation “The trend line is continuing. We are not hitting a brick wall,” Marcyk said. “One of the big worries was whether silicon oxides would work at this level.”

Chips made with these transistors will contain roughly 400 million transistors and run at 10 GHz, he said. With these chips, computers will be able to translate verbal commands or conversations from one language to another in real time, or search massive and complex optical databases.

These chips will also run on less than a volt of power, less than most of today’s notebook chips. Boot-up time, no doubt, will also improve. Current Pentium 4 chips run at 1.5 GHz and contain 42 million transistors.

The future of Moore’s Law has massive implications for the industry. For more than 30 years, semiconductor manufacturers have managed to steadily shrink the size of transistors, which has led to chips that are smaller and more powerful than their predecessors. Smaller chips also consume less energy and cost less.

In turn, this has opened the door for software developers and computer designers to create more elegant, powerful products.

Waiting to break the law Although the rule has held steady, researchers have speculated about when the laws of physics might stop it. Early in the last decade, Moore himself said the industry probably would hit a wall when transistors shrunk to around 0.25 microns, Marcyk said.

Chips with transistors that size came out in 1997 and are now old-fashioned. Most companies manufacture chips with 0.18-micron elements and will start to make 0.13-micron chips in late 2001.

Transistors of the size being discussed at the conference will show up in processors in 2005, when the 0.07-micron generation arrives, Marcyk said. The average element in these chips will measure 0.07 microns, or 70 nanometers, but some elements will be smaller.

The transistor gate, an open space inside the transistor that controls the flow of electrical current inside the transistor, will measure 30 nanometers wide. The gate walls will be three atoms thick, consisting of “an oxygen, a silicon and an oxygen atom,” Marcyk said.

For now, Intel has only managed to produce 0.07-micron generation transistors, not complete chips.

Other changes Besides shrinking, chip architecture will change in other ways. The transistors on the 0.07-micron generation of chips will be chemically printed with Extreme Ultra Violet lithography, rather than with today’s visible light lithography.

Tantalum or some other element also could replace silicon for the material in the transistor gates, although not the wafer. With a switch in materials, transistors will get wider, but they will leak less electricity, said Marcyk, making them more efficient. Transistors may also be stacked vertically rather than horizontally.

“You can get more of them in a certain area,” he said. Still, “a lot of these options are difficult to integrate.”

Convention highlights Intel will be among the many semiconductor companies and academics presenting papers at the four-day convention, which serves to showcase breakthroughs in electrical engineering and present awards to select researchers.

IBM also plans to announce that it has started production of chips that combine 0.13-micron wires, using three advanced techniques: copper wiring, silicon-on-insulator transistors, and a new type of insulating material known as a low-k dielectric.

A variety of chips are already in pilot production using the new processes, with the first customer shipments planned for early next year. IBM said chips will be made using the new processes for both its servers and other companies’ chips for networking and other gear.

IBM Research recently also announced a breakthrough design technique, called V-Groove. Should the technique be used in manufacturing, IBM says it could help create chips with parts as small as 10 nanometers or less by reducing the size of the channels between transistors. With luck, the technique could be put into production in the coming 10 to 15 years, IBM executives said.

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